atsamd11c/dac/
intenclr.rs

Help
1#[doc = "Register `INTENCLR` reader"]
2pub type R = crate::R<IntenclrSpec>;
3#[doc = "Register `INTENCLR` writer"]
4pub type W = crate::W<IntenclrSpec>;
5#[doc = "Field `UNDERRUN` reader - Underrun Interrupt Enable"]
6pub type UnderrunR = crate::BitReader;
7#[doc = "Field `UNDERRUN` writer - Underrun Interrupt Enable"]
8pub type UnderrunW<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `EMPTY` reader - Data Buffer Empty Interrupt Enable"]
10pub type EmptyR = crate::BitReader;
11#[doc = "Field `EMPTY` writer - Data Buffer Empty Interrupt Enable"]
12pub type EmptyW<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `SYNCRDY` reader - Synchronization Ready Interrupt Enable"]
14pub type SyncrdyR = crate::BitReader;
15#[doc = "Field `SYNCRDY` writer - Synchronization Ready Interrupt Enable"]
16pub type SyncrdyW<'a, REG> = crate::BitWriter<'a, REG>;
17impl R {
18    #[doc = "Bit 0 - Underrun Interrupt Enable"]
19    #[inline(always)]
20    pub fn underrun(&self) -> UnderrunR {
21        UnderrunR::new((self.bits & 1) != 0)
22    }
23    #[doc = "Bit 1 - Data Buffer Empty Interrupt Enable"]
24    #[inline(always)]
25    pub fn empty(&self) -> EmptyR {
26        EmptyR::new(((self.bits >> 1) & 1) != 0)
27    }
28    #[doc = "Bit 2 - Synchronization Ready Interrupt Enable"]
29    #[inline(always)]
30    pub fn syncrdy(&self) -> SyncrdyR {
31        SyncrdyR::new(((self.bits >> 2) & 1) != 0)
32    }
33}
34impl W {
35    #[doc = "Bit 0 - Underrun Interrupt Enable"]
36    #[inline(always)]
37    #[must_use]
38    pub fn underrun(&mut self) -> UnderrunW<IntenclrSpec> {
39        UnderrunW::new(self, 0)
40    }
41    #[doc = "Bit 1 - Data Buffer Empty Interrupt Enable"]
42    #[inline(always)]
43    #[must_use]
44    pub fn empty(&mut self) -> EmptyW<IntenclrSpec> {
45        EmptyW::new(self, 1)
46    }
47    #[doc = "Bit 2 - Synchronization Ready Interrupt Enable"]
48    #[inline(always)]
49    #[must_use]
50    pub fn syncrdy(&mut self) -> SyncrdyW<IntenclrSpec> {
51        SyncrdyW::new(self, 2)
52    }
53}
54#[doc = "Interrupt Enable Clear\n\nYou can [`read`](crate::Reg::read) this register and get [`intenclr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intenclr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
55pub struct IntenclrSpec;
56impl crate::RegisterSpec for IntenclrSpec {
57    type Ux = u8;
58}
59#[doc = "`read()` method returns [`intenclr::R`](R) reader structure"]
60impl crate::Readable for IntenclrSpec {}
61#[doc = "`write(|w| ..)` method takes [`intenclr::W`](W) writer structure"]
62impl crate::Writable for IntenclrSpec {
63    type Safety = crate::Unsafe;
64    const ZERO_TO_MODIFY_FIELDS_BITMAP: u8 = 0;
65    const ONE_TO_MODIFY_FIELDS_BITMAP: u8 = 0;
66}
67#[doc = "`reset()` method sets INTENCLR to value 0"]
68impl crate::Resettable for IntenclrSpec {
69    const RESET_VALUE: u8 = 0;
70}
atsamd11c/dac/intenclr.rs

atsamd11c/dac/
intenclr.rs
