atsamd11c/rtc/mode2/
ctrl.rs

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1#[doc = "Register `CTRL` reader"]
2pub type R = crate::R<CtrlSpec>;
3#[doc = "Register `CTRL` writer"]
4pub type W = crate::W<CtrlSpec>;
5#[doc = "Field `SWRST` reader - Software Reset"]
6pub type SwrstR = crate::BitReader;
7#[doc = "Field `SWRST` writer - Software Reset"]
8pub type SwrstW<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `ENABLE` reader - Enable"]
10pub type EnableR = crate::BitReader;
11#[doc = "Field `ENABLE` writer - Enable"]
12pub type EnableW<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Operating Mode\n\nValue on reset: 0"]
14#[derive(Clone, Copy, Debug, PartialEq, Eq)]
15#[repr(u8)]
16pub enum Modeselect {
17    #[doc = "0: Mode 0: 32-bit Counter"]
18    Count32 = 0,
19    #[doc = "1: Mode 1: 16-bit Counter"]
20    Count16 = 1,
21    #[doc = "2: Mode 2: Clock/Calendar"]
22    Clock = 2,
23}
24impl From<Modeselect> for u8 {
25    #[inline(always)]
26    fn from(variant: Modeselect) -> Self {
27        variant as _
28    }
29}
30impl crate::FieldSpec for Modeselect {
31    type Ux = u8;
32}
33impl crate::IsEnum for Modeselect {}
34#[doc = "Field `MODE` reader - Operating Mode"]
35pub type ModeR = crate::FieldReader<Modeselect>;
36impl ModeR {
37    #[doc = "Get enumerated values variant"]
38    #[inline(always)]
39    pub const fn variant(&self) -> Option<Modeselect> {
40        match self.bits {
41            0 => Some(Modeselect::Count32),
42            1 => Some(Modeselect::Count16),
43            2 => Some(Modeselect::Clock),
44            _ => None,
45        }
46    }
47    #[doc = "Mode 0: 32-bit Counter"]
48    #[inline(always)]
49    pub fn is_count32(&self) -> bool {
50        *self == Modeselect::Count32
51    }
52    #[doc = "Mode 1: 16-bit Counter"]
53    #[inline(always)]
54    pub fn is_count16(&self) -> bool {
55        *self == Modeselect::Count16
56    }
57    #[doc = "Mode 2: Clock/Calendar"]
58    #[inline(always)]
59    pub fn is_clock(&self) -> bool {
60        *self == Modeselect::Clock
61    }
62}
63#[doc = "Field `MODE` writer - Operating Mode"]
64pub type ModeW<'a, REG> = crate::FieldWriter<'a, REG, 2, Modeselect>;
65impl<'a, REG> ModeW<'a, REG>
66where
67    REG: crate::Writable + crate::RegisterSpec,
68    REG::Ux: From<u8>,
69{
70    #[doc = "Mode 0: 32-bit Counter"]
71    #[inline(always)]
72    pub fn count32(self) -> &'a mut crate::W<REG> {
73        self.variant(Modeselect::Count32)
74    }
75    #[doc = "Mode 1: 16-bit Counter"]
76    #[inline(always)]
77    pub fn count16(self) -> &'a mut crate::W<REG> {
78        self.variant(Modeselect::Count16)
79    }
80    #[doc = "Mode 2: Clock/Calendar"]
81    #[inline(always)]
82    pub fn clock(self) -> &'a mut crate::W<REG> {
83        self.variant(Modeselect::Clock)
84    }
85}
86#[doc = "Field `CLKREP` reader - Clock Representation"]
87pub type ClkrepR = crate::BitReader;
88#[doc = "Field `CLKREP` writer - Clock Representation"]
89pub type ClkrepW<'a, REG> = crate::BitWriter<'a, REG>;
90#[doc = "Field `MATCHCLR` reader - Clear on Match"]
91pub type MatchclrR = crate::BitReader;
92#[doc = "Field `MATCHCLR` writer - Clear on Match"]
93pub type MatchclrW<'a, REG> = crate::BitWriter<'a, REG>;
94#[doc = "Prescaler\n\nValue on reset: 0"]
95#[derive(Clone, Copy, Debug, PartialEq, Eq)]
96#[repr(u8)]
97pub enum Prescalerselect {
98    #[doc = "0: CLK_RTC_CNT = GCLK_RTC/1"]
99    Div1 = 0,
100    #[doc = "1: CLK_RTC_CNT = GCLK_RTC/2"]
101    Div2 = 1,
102    #[doc = "2: CLK_RTC_CNT = GCLK_RTC/4"]
103    Div4 = 2,
104    #[doc = "3: CLK_RTC_CNT = GCLK_RTC/8"]
105    Div8 = 3,
106    #[doc = "4: CLK_RTC_CNT = GCLK_RTC/16"]
107    Div16 = 4,
108    #[doc = "5: CLK_RTC_CNT = GCLK_RTC/32"]
109    Div32 = 5,
110    #[doc = "6: CLK_RTC_CNT = GCLK_RTC/64"]
111    Div64 = 6,
112    #[doc = "7: CLK_RTC_CNT = GCLK_RTC/128"]
113    Div128 = 7,
114    #[doc = "8: CLK_RTC_CNT = GCLK_RTC/256"]
115    Div256 = 8,
116    #[doc = "9: CLK_RTC_CNT = GCLK_RTC/512"]
117    Div512 = 9,
118    #[doc = "10: CLK_RTC_CNT = GCLK_RTC/1024"]
119    Div1024 = 10,
120}
121impl From<Prescalerselect> for u8 {
122    #[inline(always)]
123    fn from(variant: Prescalerselect) -> Self {
124        variant as _
125    }
126}
127impl crate::FieldSpec for Prescalerselect {
128    type Ux = u8;
129}
130impl crate::IsEnum for Prescalerselect {}
131#[doc = "Field `PRESCALER` reader - Prescaler"]
132pub type PrescalerR = crate::FieldReader<Prescalerselect>;
133impl PrescalerR {
134    #[doc = "Get enumerated values variant"]
135    #[inline(always)]
136    pub const fn variant(&self) -> Option<Prescalerselect> {
137        match self.bits {
138            0 => Some(Prescalerselect::Div1),
139            1 => Some(Prescalerselect::Div2),
140            2 => Some(Prescalerselect::Div4),
141            3 => Some(Prescalerselect::Div8),
142            4 => Some(Prescalerselect::Div16),
143            5 => Some(Prescalerselect::Div32),
144            6 => Some(Prescalerselect::Div64),
145            7 => Some(Prescalerselect::Div128),
146            8 => Some(Prescalerselect::Div256),
147            9 => Some(Prescalerselect::Div512),
148            10 => Some(Prescalerselect::Div1024),
149            _ => None,
150        }
151    }
152    #[doc = "CLK_RTC_CNT = GCLK_RTC/1"]
153    #[inline(always)]
154    pub fn is_div1(&self) -> bool {
155        *self == Prescalerselect::Div1
156    }
157    #[doc = "CLK_RTC_CNT = GCLK_RTC/2"]
158    #[inline(always)]
159    pub fn is_div2(&self) -> bool {
160        *self == Prescalerselect::Div2
161    }
162    #[doc = "CLK_RTC_CNT = GCLK_RTC/4"]
163    #[inline(always)]
164    pub fn is_div4(&self) -> bool {
165        *self == Prescalerselect::Div4
166    }
167    #[doc = "CLK_RTC_CNT = GCLK_RTC/8"]
168    #[inline(always)]
169    pub fn is_div8(&self) -> bool {
170        *self == Prescalerselect::Div8
171    }
172    #[doc = "CLK_RTC_CNT = GCLK_RTC/16"]
173    #[inline(always)]
174    pub fn is_div16(&self) -> bool {
175        *self == Prescalerselect::Div16
176    }
177    #[doc = "CLK_RTC_CNT = GCLK_RTC/32"]
178    #[inline(always)]
179    pub fn is_div32(&self) -> bool {
180        *self == Prescalerselect::Div32
181    }
182    #[doc = "CLK_RTC_CNT = GCLK_RTC/64"]
183    #[inline(always)]
184    pub fn is_div64(&self) -> bool {
185        *self == Prescalerselect::Div64
186    }
187    #[doc = "CLK_RTC_CNT = GCLK_RTC/128"]
188    #[inline(always)]
189    pub fn is_div128(&self) -> bool {
190        *self == Prescalerselect::Div128
191    }
192    #[doc = "CLK_RTC_CNT = GCLK_RTC/256"]
193    #[inline(always)]
194    pub fn is_div256(&self) -> bool {
195        *self == Prescalerselect::Div256
196    }
197    #[doc = "CLK_RTC_CNT = GCLK_RTC/512"]
198    #[inline(always)]
199    pub fn is_div512(&self) -> bool {
200        *self == Prescalerselect::Div512
201    }
202    #[doc = "CLK_RTC_CNT = GCLK_RTC/1024"]
203    #[inline(always)]
204    pub fn is_div1024(&self) -> bool {
205        *self == Prescalerselect::Div1024
206    }
207}
208#[doc = "Field `PRESCALER` writer - Prescaler"]
209pub type PrescalerW<'a, REG> = crate::FieldWriter<'a, REG, 4, Prescalerselect>;
210impl<'a, REG> PrescalerW<'a, REG>
211where
212    REG: crate::Writable + crate::RegisterSpec,
213    REG::Ux: From<u8>,
214{
215    #[doc = "CLK_RTC_CNT = GCLK_RTC/1"]
216    #[inline(always)]
217    pub fn div1(self) -> &'a mut crate::W<REG> {
218        self.variant(Prescalerselect::Div1)
219    }
220    #[doc = "CLK_RTC_CNT = GCLK_RTC/2"]
221    #[inline(always)]
222    pub fn div2(self) -> &'a mut crate::W<REG> {
223        self.variant(Prescalerselect::Div2)
224    }
225    #[doc = "CLK_RTC_CNT = GCLK_RTC/4"]
226    #[inline(always)]
227    pub fn div4(self) -> &'a mut crate::W<REG> {
228        self.variant(Prescalerselect::Div4)
229    }
230    #[doc = "CLK_RTC_CNT = GCLK_RTC/8"]
231    #[inline(always)]
232    pub fn div8(self) -> &'a mut crate::W<REG> {
233        self.variant(Prescalerselect::Div8)
234    }
235    #[doc = "CLK_RTC_CNT = GCLK_RTC/16"]
236    #[inline(always)]
237    pub fn div16(self) -> &'a mut crate::W<REG> {
238        self.variant(Prescalerselect::Div16)
239    }
240    #[doc = "CLK_RTC_CNT = GCLK_RTC/32"]
241    #[inline(always)]
242    pub fn div32(self) -> &'a mut crate::W<REG> {
243        self.variant(Prescalerselect::Div32)
244    }
245    #[doc = "CLK_RTC_CNT = GCLK_RTC/64"]
246    #[inline(always)]
247    pub fn div64(self) -> &'a mut crate::W<REG> {
248        self.variant(Prescalerselect::Div64)
249    }
250    #[doc = "CLK_RTC_CNT = GCLK_RTC/128"]
251    #[inline(always)]
252    pub fn div128(self) -> &'a mut crate::W<REG> {
253        self.variant(Prescalerselect::Div128)
254    }
255    #[doc = "CLK_RTC_CNT = GCLK_RTC/256"]
256    #[inline(always)]
257    pub fn div256(self) -> &'a mut crate::W<REG> {
258        self.variant(Prescalerselect::Div256)
259    }
260    #[doc = "CLK_RTC_CNT = GCLK_RTC/512"]
261    #[inline(always)]
262    pub fn div512(self) -> &'a mut crate::W<REG> {
263        self.variant(Prescalerselect::Div512)
264    }
265    #[doc = "CLK_RTC_CNT = GCLK_RTC/1024"]
266    #[inline(always)]
267    pub fn div1024(self) -> &'a mut crate::W<REG> {
268        self.variant(Prescalerselect::Div1024)
269    }
270}
271impl R {
272    #[doc = "Bit 0 - Software Reset"]
273    #[inline(always)]
274    pub fn swrst(&self) -> SwrstR {
275        SwrstR::new((self.bits & 1) != 0)
276    }
277    #[doc = "Bit 1 - Enable"]
278    #[inline(always)]
279    pub fn enable(&self) -> EnableR {
280        EnableR::new(((self.bits >> 1) & 1) != 0)
281    }
282    #[doc = "Bits 2:3 - Operating Mode"]
283    #[inline(always)]
284    pub fn mode(&self) -> ModeR {
285        ModeR::new(((self.bits >> 2) & 3) as u8)
286    }
287    #[doc = "Bit 6 - Clock Representation"]
288    #[inline(always)]
289    pub fn clkrep(&self) -> ClkrepR {
290        ClkrepR::new(((self.bits >> 6) & 1) != 0)
291    }
292    #[doc = "Bit 7 - Clear on Match"]
293    #[inline(always)]
294    pub fn matchclr(&self) -> MatchclrR {
295        MatchclrR::new(((self.bits >> 7) & 1) != 0)
296    }
297    #[doc = "Bits 8:11 - Prescaler"]
298    #[inline(always)]
299    pub fn prescaler(&self) -> PrescalerR {
300        PrescalerR::new(((self.bits >> 8) & 0x0f) as u8)
301    }
302}
303impl W {
304    #[doc = "Bit 0 - Software Reset"]
305    #[inline(always)]
306    #[must_use]
307    pub fn swrst(&mut self) -> SwrstW<CtrlSpec> {
308        SwrstW::new(self, 0)
309    }
310    #[doc = "Bit 1 - Enable"]
311    #[inline(always)]
312    #[must_use]
313    pub fn enable(&mut self) -> EnableW<CtrlSpec> {
314        EnableW::new(self, 1)
315    }
316    #[doc = "Bits 2:3 - Operating Mode"]
317    #[inline(always)]
318    #[must_use]
319    pub fn mode(&mut self) -> ModeW<CtrlSpec> {
320        ModeW::new(self, 2)
321    }
322    #[doc = "Bit 6 - Clock Representation"]
323    #[inline(always)]
324    #[must_use]
325    pub fn clkrep(&mut self) -> ClkrepW<CtrlSpec> {
326        ClkrepW::new(self, 6)
327    }
328    #[doc = "Bit 7 - Clear on Match"]
329    #[inline(always)]
330    #[must_use]
331    pub fn matchclr(&mut self) -> MatchclrW<CtrlSpec> {
332        MatchclrW::new(self, 7)
333    }
334    #[doc = "Bits 8:11 - Prescaler"]
335    #[inline(always)]
336    #[must_use]
337    pub fn prescaler(&mut self) -> PrescalerW<CtrlSpec> {
338        PrescalerW::new(self, 8)
339    }
340}
341#[doc = "MODE2 Control\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
342pub struct CtrlSpec;
343impl crate::RegisterSpec for CtrlSpec {
344    type Ux = u16;
345}
346#[doc = "`read()` method returns [`ctrl::R`](R) reader structure"]
347impl crate::Readable for CtrlSpec {}
348#[doc = "`write(|w| ..)` method takes [`ctrl::W`](W) writer structure"]
349impl crate::Writable for CtrlSpec {
350    type Safety = crate::Unsafe;
351    const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0;
352    const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0;
353}
354#[doc = "`reset()` method sets CTRL to value 0"]
355impl crate::Resettable for CtrlSpec {
356    const RESET_VALUE: u16 = 0;
357}
atsamd11c/rtc/mode2/ctrl.rs

atsamd11c/rtc/mode2/
ctrl.rs
