atsamd11c/sysctrl/
osc32k.rs

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1#[doc = "Register `OSC32K` reader"]
2pub type R = crate::R<Osc32kSpec>;
3#[doc = "Register `OSC32K` writer"]
4pub type W = crate::W<Osc32kSpec>;
5#[doc = "Field `ENABLE` reader - Oscillator Enable"]
6pub type EnableR = crate::BitReader;
7#[doc = "Field `ENABLE` writer - Oscillator Enable"]
8pub type EnableW<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `EN32K` reader - 32kHz Output Enable"]
10pub type En32kR = crate::BitReader;
11#[doc = "Field `EN32K` writer - 32kHz Output Enable"]
12pub type En32kW<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `EN1K` reader - 1kHz Output Enable"]
14pub type En1kR = crate::BitReader;
15#[doc = "Field `EN1K` writer - 1kHz Output Enable"]
16pub type En1kW<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `RUNSTDBY` reader - Run in Standby"]
18pub type RunstdbyR = crate::BitReader;
19#[doc = "Field `RUNSTDBY` writer - Run in Standby"]
20pub type RunstdbyW<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `ONDEMAND` reader - On Demand Control"]
22pub type OndemandR = crate::BitReader;
23#[doc = "Field `ONDEMAND` writer - On Demand Control"]
24pub type OndemandW<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `STARTUP` reader - Oscillator Start-Up Time"]
26pub type StartupR = crate::FieldReader;
27#[doc = "Field `STARTUP` writer - Oscillator Start-Up Time"]
28pub type StartupW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
29#[doc = "Field `WRTLOCK` reader - Write Lock"]
30pub type WrtlockR = crate::BitReader;
31#[doc = "Field `WRTLOCK` writer - Write Lock"]
32pub type WrtlockW<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `CALIB` reader - Oscillator Calibration"]
34pub type CalibR = crate::FieldReader;
35#[doc = "Field `CALIB` writer - Oscillator Calibration"]
36pub type CalibW<'a, REG> = crate::FieldWriter<'a, REG, 7>;
37impl R {
38    #[doc = "Bit 1 - Oscillator Enable"]
39    #[inline(always)]
40    pub fn enable(&self) -> EnableR {
41        EnableR::new(((self.bits >> 1) & 1) != 0)
42    }
43    #[doc = "Bit 2 - 32kHz Output Enable"]
44    #[inline(always)]
45    pub fn en32k(&self) -> En32kR {
46        En32kR::new(((self.bits >> 2) & 1) != 0)
47    }
48    #[doc = "Bit 3 - 1kHz Output Enable"]
49    #[inline(always)]
50    pub fn en1k(&self) -> En1kR {
51        En1kR::new(((self.bits >> 3) & 1) != 0)
52    }
53    #[doc = "Bit 6 - Run in Standby"]
54    #[inline(always)]
55    pub fn runstdby(&self) -> RunstdbyR {
56        RunstdbyR::new(((self.bits >> 6) & 1) != 0)
57    }
58    #[doc = "Bit 7 - On Demand Control"]
59    #[inline(always)]
60    pub fn ondemand(&self) -> OndemandR {
61        OndemandR::new(((self.bits >> 7) & 1) != 0)
62    }
63    #[doc = "Bits 8:10 - Oscillator Start-Up Time"]
64    #[inline(always)]
65    pub fn startup(&self) -> StartupR {
66        StartupR::new(((self.bits >> 8) & 7) as u8)
67    }
68    #[doc = "Bit 12 - Write Lock"]
69    #[inline(always)]
70    pub fn wrtlock(&self) -> WrtlockR {
71        WrtlockR::new(((self.bits >> 12) & 1) != 0)
72    }
73    #[doc = "Bits 16:22 - Oscillator Calibration"]
74    #[inline(always)]
75    pub fn calib(&self) -> CalibR {
76        CalibR::new(((self.bits >> 16) & 0x7f) as u8)
77    }
78}
79impl W {
80    #[doc = "Bit 1 - Oscillator Enable"]
81    #[inline(always)]
82    #[must_use]
83    pub fn enable(&mut self) -> EnableW<Osc32kSpec> {
84        EnableW::new(self, 1)
85    }
86    #[doc = "Bit 2 - 32kHz Output Enable"]
87    #[inline(always)]
88    #[must_use]
89    pub fn en32k(&mut self) -> En32kW<Osc32kSpec> {
90        En32kW::new(self, 2)
91    }
92    #[doc = "Bit 3 - 1kHz Output Enable"]
93    #[inline(always)]
94    #[must_use]
95    pub fn en1k(&mut self) -> En1kW<Osc32kSpec> {
96        En1kW::new(self, 3)
97    }
98    #[doc = "Bit 6 - Run in Standby"]
99    #[inline(always)]
100    #[must_use]
101    pub fn runstdby(&mut self) -> RunstdbyW<Osc32kSpec> {
102        RunstdbyW::new(self, 6)
103    }
104    #[doc = "Bit 7 - On Demand Control"]
105    #[inline(always)]
106    #[must_use]
107    pub fn ondemand(&mut self) -> OndemandW<Osc32kSpec> {
108        OndemandW::new(self, 7)
109    }
110    #[doc = "Bits 8:10 - Oscillator Start-Up Time"]
111    #[inline(always)]
112    #[must_use]
113    pub fn startup(&mut self) -> StartupW<Osc32kSpec> {
114        StartupW::new(self, 8)
115    }
116    #[doc = "Bit 12 - Write Lock"]
117    #[inline(always)]
118    #[must_use]
119    pub fn wrtlock(&mut self) -> WrtlockW<Osc32kSpec> {
120        WrtlockW::new(self, 12)
121    }
122    #[doc = "Bits 16:22 - Oscillator Calibration"]
123    #[inline(always)]
124    #[must_use]
125    pub fn calib(&mut self) -> CalibW<Osc32kSpec> {
126        CalibW::new(self, 16)
127    }
128}
129#[doc = "32kHz Internal Oscillator (OSC32K) Control\n\nYou can [`read`](crate::Reg::read) this register and get [`osc32k::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`osc32k::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
130pub struct Osc32kSpec;
131impl crate::RegisterSpec for Osc32kSpec {
132    type Ux = u32;
133}
134#[doc = "`read()` method returns [`osc32k::R`](R) reader structure"]
135impl crate::Readable for Osc32kSpec {}
136#[doc = "`write(|w| ..)` method takes [`osc32k::W`](W) writer structure"]
137impl crate::Writable for Osc32kSpec {
138    type Safety = crate::Unsafe;
139    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
140    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
141}
142#[doc = "`reset()` method sets OSC32K to value 0x003f_0080"]
143impl crate::Resettable for Osc32kSpec {
144    const RESET_VALUE: u32 = 0x003f_0080;
145}
atsamd11c/sysctrl/osc32k.rs

atsamd11c/sysctrl/
osc32k.rs
