atsamd11c/adc/
ctrlb.rs

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1#[doc = "Register `CTRLB` reader"]
2pub type R = crate::R<CtrlbSpec>;
3#[doc = "Register `CTRLB` writer"]
4pub type W = crate::W<CtrlbSpec>;
5#[doc = "Field `DIFFMODE` reader - Differential Mode"]
6pub type DiffmodeR = crate::BitReader;
7#[doc = "Field `DIFFMODE` writer - Differential Mode"]
8pub type DiffmodeW<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `LEFTADJ` reader - Left-Adjusted Result"]
10pub type LeftadjR = crate::BitReader;
11#[doc = "Field `LEFTADJ` writer - Left-Adjusted Result"]
12pub type LeftadjW<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `FREERUN` reader - Free Running Mode"]
14pub type FreerunR = crate::BitReader;
15#[doc = "Field `FREERUN` writer - Free Running Mode"]
16pub type FreerunW<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `CORREN` reader - Digital Correction Logic Enabled"]
18pub type CorrenR = crate::BitReader;
19#[doc = "Field `CORREN` writer - Digital Correction Logic Enabled"]
20pub type CorrenW<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Conversion Result Resolution\n\nValue on reset: 0"]
22#[derive(Clone, Copy, Debug, PartialEq, Eq)]
23#[repr(u8)]
24pub enum Resselselect {
25    #[doc = "0: 12-bit result"]
26    _12bit = 0,
27    #[doc = "1: For averaging mode output"]
28    _16bit = 1,
29    #[doc = "2: 10-bit result"]
30    _10bit = 2,
31    #[doc = "3: 8-bit result"]
32    _8bit = 3,
33}
34impl From<Resselselect> for u8 {
35    #[inline(always)]
36    fn from(variant: Resselselect) -> Self {
37        variant as _
38    }
39}
40impl crate::FieldSpec for Resselselect {
41    type Ux = u8;
42}
43impl crate::IsEnum for Resselselect {}
44#[doc = "Field `RESSEL` reader - Conversion Result Resolution"]
45pub type ResselR = crate::FieldReader<Resselselect>;
46impl ResselR {
47    #[doc = "Get enumerated values variant"]
48    #[inline(always)]
49    pub const fn variant(&self) -> Resselselect {
50        match self.bits {
51            0 => Resselselect::_12bit,
52            1 => Resselselect::_16bit,
53            2 => Resselselect::_10bit,
54            3 => Resselselect::_8bit,
55            _ => unreachable!(),
56        }
57    }
58    #[doc = "12-bit result"]
59    #[inline(always)]
60    pub fn is_12bit(&self) -> bool {
61        *self == Resselselect::_12bit
62    }
63    #[doc = "For averaging mode output"]
64    #[inline(always)]
65    pub fn is_16bit(&self) -> bool {
66        *self == Resselselect::_16bit
67    }
68    #[doc = "10-bit result"]
69    #[inline(always)]
70    pub fn is_10bit(&self) -> bool {
71        *self == Resselselect::_10bit
72    }
73    #[doc = "8-bit result"]
74    #[inline(always)]
75    pub fn is_8bit(&self) -> bool {
76        *self == Resselselect::_8bit
77    }
78}
79#[doc = "Field `RESSEL` writer - Conversion Result Resolution"]
80pub type ResselW<'a, REG> = crate::FieldWriter<'a, REG, 2, Resselselect, crate::Safe>;
81impl<'a, REG> ResselW<'a, REG>
82where
83    REG: crate::Writable + crate::RegisterSpec,
84    REG::Ux: From<u8>,
85{
86    #[doc = "12-bit result"]
87    #[inline(always)]
88    pub fn _12bit(self) -> &'a mut crate::W<REG> {
89        self.variant(Resselselect::_12bit)
90    }
91    #[doc = "For averaging mode output"]
92    #[inline(always)]
93    pub fn _16bit(self) -> &'a mut crate::W<REG> {
94        self.variant(Resselselect::_16bit)
95    }
96    #[doc = "10-bit result"]
97    #[inline(always)]
98    pub fn _10bit(self) -> &'a mut crate::W<REG> {
99        self.variant(Resselselect::_10bit)
100    }
101    #[doc = "8-bit result"]
102    #[inline(always)]
103    pub fn _8bit(self) -> &'a mut crate::W<REG> {
104        self.variant(Resselselect::_8bit)
105    }
106}
107#[doc = "Prescaler Configuration\n\nValue on reset: 0"]
108#[derive(Clone, Copy, Debug, PartialEq, Eq)]
109#[repr(u8)]
110pub enum Prescalerselect {
111    #[doc = "0: Peripheral clock divided by 4"]
112    Div4 = 0,
113    #[doc = "1: Peripheral clock divided by 8"]
114    Div8 = 1,
115    #[doc = "2: Peripheral clock divided by 16"]
116    Div16 = 2,
117    #[doc = "3: Peripheral clock divided by 32"]
118    Div32 = 3,
119    #[doc = "4: Peripheral clock divided by 64"]
120    Div64 = 4,
121    #[doc = "5: Peripheral clock divided by 128"]
122    Div128 = 5,
123    #[doc = "6: Peripheral clock divided by 256"]
124    Div256 = 6,
125    #[doc = "7: Peripheral clock divided by 512"]
126    Div512 = 7,
127}
128impl From<Prescalerselect> for u8 {
129    #[inline(always)]
130    fn from(variant: Prescalerselect) -> Self {
131        variant as _
132    }
133}
134impl crate::FieldSpec for Prescalerselect {
135    type Ux = u8;
136}
137impl crate::IsEnum for Prescalerselect {}
138#[doc = "Field `PRESCALER` reader - Prescaler Configuration"]
139pub type PrescalerR = crate::FieldReader<Prescalerselect>;
140impl PrescalerR {
141    #[doc = "Get enumerated values variant"]
142    #[inline(always)]
143    pub const fn variant(&self) -> Prescalerselect {
144        match self.bits {
145            0 => Prescalerselect::Div4,
146            1 => Prescalerselect::Div8,
147            2 => Prescalerselect::Div16,
148            3 => Prescalerselect::Div32,
149            4 => Prescalerselect::Div64,
150            5 => Prescalerselect::Div128,
151            6 => Prescalerselect::Div256,
152            7 => Prescalerselect::Div512,
153            _ => unreachable!(),
154        }
155    }
156    #[doc = "Peripheral clock divided by 4"]
157    #[inline(always)]
158    pub fn is_div4(&self) -> bool {
159        *self == Prescalerselect::Div4
160    }
161    #[doc = "Peripheral clock divided by 8"]
162    #[inline(always)]
163    pub fn is_div8(&self) -> bool {
164        *self == Prescalerselect::Div8
165    }
166    #[doc = "Peripheral clock divided by 16"]
167    #[inline(always)]
168    pub fn is_div16(&self) -> bool {
169        *self == Prescalerselect::Div16
170    }
171    #[doc = "Peripheral clock divided by 32"]
172    #[inline(always)]
173    pub fn is_div32(&self) -> bool {
174        *self == Prescalerselect::Div32
175    }
176    #[doc = "Peripheral clock divided by 64"]
177    #[inline(always)]
178    pub fn is_div64(&self) -> bool {
179        *self == Prescalerselect::Div64
180    }
181    #[doc = "Peripheral clock divided by 128"]
182    #[inline(always)]
183    pub fn is_div128(&self) -> bool {
184        *self == Prescalerselect::Div128
185    }
186    #[doc = "Peripheral clock divided by 256"]
187    #[inline(always)]
188    pub fn is_div256(&self) -> bool {
189        *self == Prescalerselect::Div256
190    }
191    #[doc = "Peripheral clock divided by 512"]
192    #[inline(always)]
193    pub fn is_div512(&self) -> bool {
194        *self == Prescalerselect::Div512
195    }
196}
197#[doc = "Field `PRESCALER` writer - Prescaler Configuration"]
198pub type PrescalerW<'a, REG> = crate::FieldWriter<'a, REG, 3, Prescalerselect, crate::Safe>;
199impl<'a, REG> PrescalerW<'a, REG>
200where
201    REG: crate::Writable + crate::RegisterSpec,
202    REG::Ux: From<u8>,
203{
204    #[doc = "Peripheral clock divided by 4"]
205    #[inline(always)]
206    pub fn div4(self) -> &'a mut crate::W<REG> {
207        self.variant(Prescalerselect::Div4)
208    }
209    #[doc = "Peripheral clock divided by 8"]
210    #[inline(always)]
211    pub fn div8(self) -> &'a mut crate::W<REG> {
212        self.variant(Prescalerselect::Div8)
213    }
214    #[doc = "Peripheral clock divided by 16"]
215    #[inline(always)]
216    pub fn div16(self) -> &'a mut crate::W<REG> {
217        self.variant(Prescalerselect::Div16)
218    }
219    #[doc = "Peripheral clock divided by 32"]
220    #[inline(always)]
221    pub fn div32(self) -> &'a mut crate::W<REG> {
222        self.variant(Prescalerselect::Div32)
223    }
224    #[doc = "Peripheral clock divided by 64"]
225    #[inline(always)]
226    pub fn div64(self) -> &'a mut crate::W<REG> {
227        self.variant(Prescalerselect::Div64)
228    }
229    #[doc = "Peripheral clock divided by 128"]
230    #[inline(always)]
231    pub fn div128(self) -> &'a mut crate::W<REG> {
232        self.variant(Prescalerselect::Div128)
233    }
234    #[doc = "Peripheral clock divided by 256"]
235    #[inline(always)]
236    pub fn div256(self) -> &'a mut crate::W<REG> {
237        self.variant(Prescalerselect::Div256)
238    }
239    #[doc = "Peripheral clock divided by 512"]
240    #[inline(always)]
241    pub fn div512(self) -> &'a mut crate::W<REG> {
242        self.variant(Prescalerselect::Div512)
243    }
244}
245impl R {
246    #[doc = "Bit 0 - Differential Mode"]
247    #[inline(always)]
248    pub fn diffmode(&self) -> DiffmodeR {
249        DiffmodeR::new((self.bits & 1) != 0)
250    }
251    #[doc = "Bit 1 - Left-Adjusted Result"]
252    #[inline(always)]
253    pub fn leftadj(&self) -> LeftadjR {
254        LeftadjR::new(((self.bits >> 1) & 1) != 0)
255    }
256    #[doc = "Bit 2 - Free Running Mode"]
257    #[inline(always)]
258    pub fn freerun(&self) -> FreerunR {
259        FreerunR::new(((self.bits >> 2) & 1) != 0)
260    }
261    #[doc = "Bit 3 - Digital Correction Logic Enabled"]
262    #[inline(always)]
263    pub fn corren(&self) -> CorrenR {
264        CorrenR::new(((self.bits >> 3) & 1) != 0)
265    }
266    #[doc = "Bits 4:5 - Conversion Result Resolution"]
267    #[inline(always)]
268    pub fn ressel(&self) -> ResselR {
269        ResselR::new(((self.bits >> 4) & 3) as u8)
270    }
271    #[doc = "Bits 8:10 - Prescaler Configuration"]
272    #[inline(always)]
273    pub fn prescaler(&self) -> PrescalerR {
274        PrescalerR::new(((self.bits >> 8) & 7) as u8)
275    }
276}
277impl W {
278    #[doc = "Bit 0 - Differential Mode"]
279    #[inline(always)]
280    #[must_use]
281    pub fn diffmode(&mut self) -> DiffmodeW<CtrlbSpec> {
282        DiffmodeW::new(self, 0)
283    }
284    #[doc = "Bit 1 - Left-Adjusted Result"]
285    #[inline(always)]
286    #[must_use]
287    pub fn leftadj(&mut self) -> LeftadjW<CtrlbSpec> {
288        LeftadjW::new(self, 1)
289    }
290    #[doc = "Bit 2 - Free Running Mode"]
291    #[inline(always)]
292    #[must_use]
293    pub fn freerun(&mut self) -> FreerunW<CtrlbSpec> {
294        FreerunW::new(self, 2)
295    }
296    #[doc = "Bit 3 - Digital Correction Logic Enabled"]
297    #[inline(always)]
298    #[must_use]
299    pub fn corren(&mut self) -> CorrenW<CtrlbSpec> {
300        CorrenW::new(self, 3)
301    }
302    #[doc = "Bits 4:5 - Conversion Result Resolution"]
303    #[inline(always)]
304    #[must_use]
305    pub fn ressel(&mut self) -> ResselW<CtrlbSpec> {
306        ResselW::new(self, 4)
307    }
308    #[doc = "Bits 8:10 - Prescaler Configuration"]
309    #[inline(always)]
310    #[must_use]
311    pub fn prescaler(&mut self) -> PrescalerW<CtrlbSpec> {
312        PrescalerW::new(self, 8)
313    }
314}
315#[doc = "Control B\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrlb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrlb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
316pub struct CtrlbSpec;
317impl crate::RegisterSpec for CtrlbSpec {
318    type Ux = u16;
319}
320#[doc = "`read()` method returns [`ctrlb::R`](R) reader structure"]
321impl crate::Readable for CtrlbSpec {}
322#[doc = "`write(|w| ..)` method takes [`ctrlb::W`](W) writer structure"]
323impl crate::Writable for CtrlbSpec {
324    type Safety = crate::Unsafe;
325    const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0;
326    const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0;
327}
328#[doc = "`reset()` method sets CTRLB to value 0"]
329impl crate::Resettable for CtrlbSpec {
330    const RESET_VALUE: u16 = 0;
331}
atsamd11c/adc/ctrlb.rs

atsamd11c/adc/
ctrlb.rs
