atsamd11c/gclk/
genctrl.rs

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1#[doc = "Register `GENCTRL` reader"]
2pub type R = crate::R<GenctrlSpec>;
3#[doc = "Register `GENCTRL` writer"]
4pub type W = crate::W<GenctrlSpec>;
5#[doc = "Field `ID` reader - Generic Clock Generator Selection"]
6pub type IdR = crate::FieldReader;
7#[doc = "Field `ID` writer - Generic Clock Generator Selection"]
8pub type IdW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
9#[doc = "Source Select\n\nValue on reset: 0"]
10#[derive(Clone, Copy, Debug, PartialEq, Eq)]
11#[repr(u8)]
12pub enum Srcselect {
13    #[doc = "0: XOSC oscillator output"]
14    Xosc = 0,
15    #[doc = "1: Generator input pad"]
16    Gclkin = 1,
17    #[doc = "2: Generic clock generator 1 output"]
18    Gclkgen1 = 2,
19    #[doc = "3: OSCULP32K oscillator output"]
20    Osculp32k = 3,
21    #[doc = "4: OSC32K oscillator output"]
22    Osc32k = 4,
23    #[doc = "5: XOSC32K oscillator output"]
24    Xosc32k = 5,
25    #[doc = "6: OSC8M oscillator output"]
26    Osc8m = 6,
27    #[doc = "7: DFLL48M output"]
28    Dfll48m = 7,
29    #[doc = "8: DPLL96M output"]
30    Dpll96m = 8,
31}
32impl From<Srcselect> for u8 {
33    #[inline(always)]
34    fn from(variant: Srcselect) -> Self {
35        variant as _
36    }
37}
38impl crate::FieldSpec for Srcselect {
39    type Ux = u8;
40}
41impl crate::IsEnum for Srcselect {}
42#[doc = "Field `SRC` reader - Source Select"]
43pub type SrcR = crate::FieldReader<Srcselect>;
44impl SrcR {
45    #[doc = "Get enumerated values variant"]
46    #[inline(always)]
47    pub const fn variant(&self) -> Option<Srcselect> {
48        match self.bits {
49            0 => Some(Srcselect::Xosc),
50            1 => Some(Srcselect::Gclkin),
51            2 => Some(Srcselect::Gclkgen1),
52            3 => Some(Srcselect::Osculp32k),
53            4 => Some(Srcselect::Osc32k),
54            5 => Some(Srcselect::Xosc32k),
55            6 => Some(Srcselect::Osc8m),
56            7 => Some(Srcselect::Dfll48m),
57            8 => Some(Srcselect::Dpll96m),
58            _ => None,
59        }
60    }
61    #[doc = "XOSC oscillator output"]
62    #[inline(always)]
63    pub fn is_xosc(&self) -> bool {
64        *self == Srcselect::Xosc
65    }
66    #[doc = "Generator input pad"]
67    #[inline(always)]
68    pub fn is_gclkin(&self) -> bool {
69        *self == Srcselect::Gclkin
70    }
71    #[doc = "Generic clock generator 1 output"]
72    #[inline(always)]
73    pub fn is_gclkgen1(&self) -> bool {
74        *self == Srcselect::Gclkgen1
75    }
76    #[doc = "OSCULP32K oscillator output"]
77    #[inline(always)]
78    pub fn is_osculp32k(&self) -> bool {
79        *self == Srcselect::Osculp32k
80    }
81    #[doc = "OSC32K oscillator output"]
82    #[inline(always)]
83    pub fn is_osc32k(&self) -> bool {
84        *self == Srcselect::Osc32k
85    }
86    #[doc = "XOSC32K oscillator output"]
87    #[inline(always)]
88    pub fn is_xosc32k(&self) -> bool {
89        *self == Srcselect::Xosc32k
90    }
91    #[doc = "OSC8M oscillator output"]
92    #[inline(always)]
93    pub fn is_osc8m(&self) -> bool {
94        *self == Srcselect::Osc8m
95    }
96    #[doc = "DFLL48M output"]
97    #[inline(always)]
98    pub fn is_dfll48m(&self) -> bool {
99        *self == Srcselect::Dfll48m
100    }
101    #[doc = "DPLL96M output"]
102    #[inline(always)]
103    pub fn is_dpll96m(&self) -> bool {
104        *self == Srcselect::Dpll96m
105    }
106}
107#[doc = "Field `SRC` writer - Source Select"]
108pub type SrcW<'a, REG> = crate::FieldWriter<'a, REG, 5, Srcselect>;
109impl<'a, REG> SrcW<'a, REG>
110where
111    REG: crate::Writable + crate::RegisterSpec,
112    REG::Ux: From<u8>,
113{
114    #[doc = "XOSC oscillator output"]
115    #[inline(always)]
116    pub fn xosc(self) -> &'a mut crate::W<REG> {
117        self.variant(Srcselect::Xosc)
118    }
119    #[doc = "Generator input pad"]
120    #[inline(always)]
121    pub fn gclkin(self) -> &'a mut crate::W<REG> {
122        self.variant(Srcselect::Gclkin)
123    }
124    #[doc = "Generic clock generator 1 output"]
125    #[inline(always)]
126    pub fn gclkgen1(self) -> &'a mut crate::W<REG> {
127        self.variant(Srcselect::Gclkgen1)
128    }
129    #[doc = "OSCULP32K oscillator output"]
130    #[inline(always)]
131    pub fn osculp32k(self) -> &'a mut crate::W<REG> {
132        self.variant(Srcselect::Osculp32k)
133    }
134    #[doc = "OSC32K oscillator output"]
135    #[inline(always)]
136    pub fn osc32k(self) -> &'a mut crate::W<REG> {
137        self.variant(Srcselect::Osc32k)
138    }
139    #[doc = "XOSC32K oscillator output"]
140    #[inline(always)]
141    pub fn xosc32k(self) -> &'a mut crate::W<REG> {
142        self.variant(Srcselect::Xosc32k)
143    }
144    #[doc = "OSC8M oscillator output"]
145    #[inline(always)]
146    pub fn osc8m(self) -> &'a mut crate::W<REG> {
147        self.variant(Srcselect::Osc8m)
148    }
149    #[doc = "DFLL48M output"]
150    #[inline(always)]
151    pub fn dfll48m(self) -> &'a mut crate::W<REG> {
152        self.variant(Srcselect::Dfll48m)
153    }
154    #[doc = "DPLL96M output"]
155    #[inline(always)]
156    pub fn dpll96m(self) -> &'a mut crate::W<REG> {
157        self.variant(Srcselect::Dpll96m)
158    }
159}
160#[doc = "Field `GENEN` reader - Generic Clock Generator Enable"]
161pub type GenenR = crate::BitReader;
162#[doc = "Field `GENEN` writer - Generic Clock Generator Enable"]
163pub type GenenW<'a, REG> = crate::BitWriter<'a, REG>;
164#[doc = "Field `IDC` reader - Improve Duty Cycle"]
165pub type IdcR = crate::BitReader;
166#[doc = "Field `IDC` writer - Improve Duty Cycle"]
167pub type IdcW<'a, REG> = crate::BitWriter<'a, REG>;
168#[doc = "Field `OOV` reader - Output Off Value"]
169pub type OovR = crate::BitReader;
170#[doc = "Field `OOV` writer - Output Off Value"]
171pub type OovW<'a, REG> = crate::BitWriter<'a, REG>;
172#[doc = "Field `OE` reader - Output Enable"]
173pub type OeR = crate::BitReader;
174#[doc = "Field `OE` writer - Output Enable"]
175pub type OeW<'a, REG> = crate::BitWriter<'a, REG>;
176#[doc = "Field `DIVSEL` reader - Divide Selection"]
177pub type DivselR = crate::BitReader;
178#[doc = "Field `DIVSEL` writer - Divide Selection"]
179pub type DivselW<'a, REG> = crate::BitWriter<'a, REG>;
180#[doc = "Field `RUNSTDBY` reader - Run in Standby"]
181pub type RunstdbyR = crate::BitReader;
182#[doc = "Field `RUNSTDBY` writer - Run in Standby"]
183pub type RunstdbyW<'a, REG> = crate::BitWriter<'a, REG>;
184impl R {
185    #[doc = "Bits 0:3 - Generic Clock Generator Selection"]
186    #[inline(always)]
187    pub fn id(&self) -> IdR {
188        IdR::new((self.bits & 0x0f) as u8)
189    }
190    #[doc = "Bits 8:12 - Source Select"]
191    #[inline(always)]
192    pub fn src(&self) -> SrcR {
193        SrcR::new(((self.bits >> 8) & 0x1f) as u8)
194    }
195    #[doc = "Bit 16 - Generic Clock Generator Enable"]
196    #[inline(always)]
197    pub fn genen(&self) -> GenenR {
198        GenenR::new(((self.bits >> 16) & 1) != 0)
199    }
200    #[doc = "Bit 17 - Improve Duty Cycle"]
201    #[inline(always)]
202    pub fn idc(&self) -> IdcR {
203        IdcR::new(((self.bits >> 17) & 1) != 0)
204    }
205    #[doc = "Bit 18 - Output Off Value"]
206    #[inline(always)]
207    pub fn oov(&self) -> OovR {
208        OovR::new(((self.bits >> 18) & 1) != 0)
209    }
210    #[doc = "Bit 19 - Output Enable"]
211    #[inline(always)]
212    pub fn oe(&self) -> OeR {
213        OeR::new(((self.bits >> 19) & 1) != 0)
214    }
215    #[doc = "Bit 20 - Divide Selection"]
216    #[inline(always)]
217    pub fn divsel(&self) -> DivselR {
218        DivselR::new(((self.bits >> 20) & 1) != 0)
219    }
220    #[doc = "Bit 21 - Run in Standby"]
221    #[inline(always)]
222    pub fn runstdby(&self) -> RunstdbyR {
223        RunstdbyR::new(((self.bits >> 21) & 1) != 0)
224    }
225}
226impl W {
227    #[doc = "Bits 0:3 - Generic Clock Generator Selection"]
228    #[inline(always)]
229    #[must_use]
230    pub fn id(&mut self) -> IdW<GenctrlSpec> {
231        IdW::new(self, 0)
232    }
233    #[doc = "Bits 8:12 - Source Select"]
234    #[inline(always)]
235    #[must_use]
236    pub fn src(&mut self) -> SrcW<GenctrlSpec> {
237        SrcW::new(self, 8)
238    }
239    #[doc = "Bit 16 - Generic Clock Generator Enable"]
240    #[inline(always)]
241    #[must_use]
242    pub fn genen(&mut self) -> GenenW<GenctrlSpec> {
243        GenenW::new(self, 16)
244    }
245    #[doc = "Bit 17 - Improve Duty Cycle"]
246    #[inline(always)]
247    #[must_use]
248    pub fn idc(&mut self) -> IdcW<GenctrlSpec> {
249        IdcW::new(self, 17)
250    }
251    #[doc = "Bit 18 - Output Off Value"]
252    #[inline(always)]
253    #[must_use]
254    pub fn oov(&mut self) -> OovW<GenctrlSpec> {
255        OovW::new(self, 18)
256    }
257    #[doc = "Bit 19 - Output Enable"]
258    #[inline(always)]
259    #[must_use]
260    pub fn oe(&mut self) -> OeW<GenctrlSpec> {
261        OeW::new(self, 19)
262    }
263    #[doc = "Bit 20 - Divide Selection"]
264    #[inline(always)]
265    #[must_use]
266    pub fn divsel(&mut self) -> DivselW<GenctrlSpec> {
267        DivselW::new(self, 20)
268    }
269    #[doc = "Bit 21 - Run in Standby"]
270    #[inline(always)]
271    #[must_use]
272    pub fn runstdby(&mut self) -> RunstdbyW<GenctrlSpec> {
273        RunstdbyW::new(self, 21)
274    }
275}
276#[doc = "Generic Clock Generator Control\n\nYou can [`read`](crate::Reg::read) this register and get [`genctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`genctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
277pub struct GenctrlSpec;
278impl crate::RegisterSpec for GenctrlSpec {
279    type Ux = u32;
280}
281#[doc = "`read()` method returns [`genctrl::R`](R) reader structure"]
282impl crate::Readable for GenctrlSpec {}
283#[doc = "`write(|w| ..)` method takes [`genctrl::W`](W) writer structure"]
284impl crate::Writable for GenctrlSpec {
285    type Safety = crate::Unsafe;
286    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
287    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
288}
289#[doc = "`reset()` method sets GENCTRL to value 0"]
290impl crate::Resettable for GenctrlSpec {
291    const RESET_VALUE: u32 = 0;
292}
atsamd11c/gclk/genctrl.rs

atsamd11c/gclk/
genctrl.rs
