atsamd11c/tcc0/
wexctrl.rs

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1#[doc = "Register `WEXCTRL` reader"]
2pub type R = crate::R<WexctrlSpec>;
3#[doc = "Register `WEXCTRL` writer"]
4pub type W = crate::W<WexctrlSpec>;
5#[doc = "Field `OTMX` reader - Output Matrix"]
6pub type OtmxR = crate::FieldReader;
7#[doc = "Field `OTMX` writer - Output Matrix"]
8pub type OtmxW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
9#[doc = "Field `DTIEN0` reader - Dead-time Insertion Generator 0 Enable"]
10pub type Dtien0R = crate::BitReader;
11#[doc = "Field `DTIEN0` writer - Dead-time Insertion Generator 0 Enable"]
12pub type Dtien0W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `DTIEN1` reader - Dead-time Insertion Generator 1 Enable"]
14pub type Dtien1R = crate::BitReader;
15#[doc = "Field `DTIEN1` writer - Dead-time Insertion Generator 1 Enable"]
16pub type Dtien1W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `DTIEN2` reader - Dead-time Insertion Generator 2 Enable"]
18pub type Dtien2R = crate::BitReader;
19#[doc = "Field `DTIEN2` writer - Dead-time Insertion Generator 2 Enable"]
20pub type Dtien2W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `DTIEN3` reader - Dead-time Insertion Generator 3 Enable"]
22pub type Dtien3R = crate::BitReader;
23#[doc = "Field `DTIEN3` writer - Dead-time Insertion Generator 3 Enable"]
24pub type Dtien3W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `DTLS` reader - Dead-time Low Side Outputs Value"]
26pub type DtlsR = crate::FieldReader;
27#[doc = "Field `DTLS` writer - Dead-time Low Side Outputs Value"]
28pub type DtlsW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
29#[doc = "Field `DTHS` reader - Dead-time High Side Outputs Value"]
30pub type DthsR = crate::FieldReader;
31#[doc = "Field `DTHS` writer - Dead-time High Side Outputs Value"]
32pub type DthsW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
33impl R {
34    #[doc = "Bits 0:1 - Output Matrix"]
35    #[inline(always)]
36    pub fn otmx(&self) -> OtmxR {
37        OtmxR::new((self.bits & 3) as u8)
38    }
39    #[doc = "Bit 8 - Dead-time Insertion Generator 0 Enable"]
40    #[inline(always)]
41    pub fn dtien0(&self) -> Dtien0R {
42        Dtien0R::new(((self.bits >> 8) & 1) != 0)
43    }
44    #[doc = "Bit 9 - Dead-time Insertion Generator 1 Enable"]
45    #[inline(always)]
46    pub fn dtien1(&self) -> Dtien1R {
47        Dtien1R::new(((self.bits >> 9) & 1) != 0)
48    }
49    #[doc = "Bit 10 - Dead-time Insertion Generator 2 Enable"]
50    #[inline(always)]
51    pub fn dtien2(&self) -> Dtien2R {
52        Dtien2R::new(((self.bits >> 10) & 1) != 0)
53    }
54    #[doc = "Bit 11 - Dead-time Insertion Generator 3 Enable"]
55    #[inline(always)]
56    pub fn dtien3(&self) -> Dtien3R {
57        Dtien3R::new(((self.bits >> 11) & 1) != 0)
58    }
59    #[doc = "Bits 16:23 - Dead-time Low Side Outputs Value"]
60    #[inline(always)]
61    pub fn dtls(&self) -> DtlsR {
62        DtlsR::new(((self.bits >> 16) & 0xff) as u8)
63    }
64    #[doc = "Bits 24:31 - Dead-time High Side Outputs Value"]
65    #[inline(always)]
66    pub fn dths(&self) -> DthsR {
67        DthsR::new(((self.bits >> 24) & 0xff) as u8)
68    }
69}
70impl W {
71    #[doc = "Bits 0:1 - Output Matrix"]
72    #[inline(always)]
73    #[must_use]
74    pub fn otmx(&mut self) -> OtmxW<WexctrlSpec> {
75        OtmxW::new(self, 0)
76    }
77    #[doc = "Bit 8 - Dead-time Insertion Generator 0 Enable"]
78    #[inline(always)]
79    #[must_use]
80    pub fn dtien0(&mut self) -> Dtien0W<WexctrlSpec> {
81        Dtien0W::new(self, 8)
82    }
83    #[doc = "Bit 9 - Dead-time Insertion Generator 1 Enable"]
84    #[inline(always)]
85    #[must_use]
86    pub fn dtien1(&mut self) -> Dtien1W<WexctrlSpec> {
87        Dtien1W::new(self, 9)
88    }
89    #[doc = "Bit 10 - Dead-time Insertion Generator 2 Enable"]
90    #[inline(always)]
91    #[must_use]
92    pub fn dtien2(&mut self) -> Dtien2W<WexctrlSpec> {
93        Dtien2W::new(self, 10)
94    }
95    #[doc = "Bit 11 - Dead-time Insertion Generator 3 Enable"]
96    #[inline(always)]
97    #[must_use]
98    pub fn dtien3(&mut self) -> Dtien3W<WexctrlSpec> {
99        Dtien3W::new(self, 11)
100    }
101    #[doc = "Bits 16:23 - Dead-time Low Side Outputs Value"]
102    #[inline(always)]
103    #[must_use]
104    pub fn dtls(&mut self) -> DtlsW<WexctrlSpec> {
105        DtlsW::new(self, 16)
106    }
107    #[doc = "Bits 24:31 - Dead-time High Side Outputs Value"]
108    #[inline(always)]
109    #[must_use]
110    pub fn dths(&mut self) -> DthsW<WexctrlSpec> {
111        DthsW::new(self, 24)
112    }
113}
114#[doc = "Waveform Extension Configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`wexctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wexctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
115pub struct WexctrlSpec;
116impl crate::RegisterSpec for WexctrlSpec {
117    type Ux = u32;
118}
119#[doc = "`read()` method returns [`wexctrl::R`](R) reader structure"]
120impl crate::Readable for WexctrlSpec {}
121#[doc = "`write(|w| ..)` method takes [`wexctrl::W`](W) writer structure"]
122impl crate::Writable for WexctrlSpec {
123    type Safety = crate::Unsafe;
124    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
125    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
126}
127#[doc = "`reset()` method sets WEXCTRL to value 0"]
128impl crate::Resettable for WexctrlSpec {
129    const RESET_VALUE: u32 = 0;
130}
atsamd11c/tcc0/wexctrl.rs

atsamd11c/tcc0/
wexctrl.rs
