atsamd11c/sercom0/usart/
ctrla.rs

1#[doc = "Register `CTRLA` reader"]
2pub type R = crate::R<CtrlaSpec>;
3#[doc = "Register `CTRLA` writer"]
4pub type W = crate::W<CtrlaSpec>;
5#[doc = "Field `SWRST` reader - Software Reset"]
6pub type SwrstR = crate::BitReader;
7#[doc = "Field `SWRST` writer - Software Reset"]
8pub type SwrstW<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `ENABLE` reader - Enable"]
10pub type EnableR = crate::BitReader;
11#[doc = "Field `ENABLE` writer - Enable"]
12pub type EnableW<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Operating Mode\n\nValue on reset: 0"]
14#[derive(Clone, Copy, Debug, PartialEq, Eq)]
15#[repr(u8)]
16pub enum Modeselect {
17    #[doc = "0: USART mode with external clock"]
18    UsartExtClk = 0,
19    #[doc = "1: USART mode with internal clock"]
20    UsartIntClk = 1,
21    #[doc = "2: SPI mode with external clock"]
22    SpiSlave = 2,
23    #[doc = "3: SPI mode with internal clock"]
24    SpiMaster = 3,
25    #[doc = "4: I2C mode with external clock"]
26    I2cSlave = 4,
27    #[doc = "5: I2C mode with internal clock"]
28    I2cMaster = 5,
29}
30impl From<Modeselect> for u8 {
31    #[inline(always)]
32    fn from(variant: Modeselect) -> Self {
33        variant as _
34    }
35}
36impl crate::FieldSpec for Modeselect {
37    type Ux = u8;
38}
39impl crate::IsEnum for Modeselect {}
40#[doc = "Field `MODE` reader - Operating Mode"]
41pub type ModeR = crate::FieldReader<Modeselect>;
42impl ModeR {
43    #[doc = "Get enumerated values variant"]
44    #[inline(always)]
45    pub const fn variant(&self) -> Option<Modeselect> {
46        match self.bits {
47            0 => Some(Modeselect::UsartExtClk),
48            1 => Some(Modeselect::UsartIntClk),
49            2 => Some(Modeselect::SpiSlave),
50            3 => Some(Modeselect::SpiMaster),
51            4 => Some(Modeselect::I2cSlave),
52            5 => Some(Modeselect::I2cMaster),
53            _ => None,
54        }
55    }
56    #[doc = "USART mode with external clock"]
57    #[inline(always)]
58    pub fn is_usart_ext_clk(&self) -> bool {
59        *self == Modeselect::UsartExtClk
60    }
61    #[doc = "USART mode with internal clock"]
62    #[inline(always)]
63    pub fn is_usart_int_clk(&self) -> bool {
64        *self == Modeselect::UsartIntClk
65    }
66    #[doc = "SPI mode with external clock"]
67    #[inline(always)]
68    pub fn is_spi_slave(&self) -> bool {
69        *self == Modeselect::SpiSlave
70    }
71    #[doc = "SPI mode with internal clock"]
72    #[inline(always)]
73    pub fn is_spi_master(&self) -> bool {
74        *self == Modeselect::SpiMaster
75    }
76    #[doc = "I2C mode with external clock"]
77    #[inline(always)]
78    pub fn is_i2c_slave(&self) -> bool {
79        *self == Modeselect::I2cSlave
80    }
81    #[doc = "I2C mode with internal clock"]
82    #[inline(always)]
83    pub fn is_i2c_master(&self) -> bool {
84        *self == Modeselect::I2cMaster
85    }
86}
87#[doc = "Field `MODE` writer - Operating Mode"]
88pub type ModeW<'a, REG> = crate::FieldWriter<'a, REG, 3, Modeselect>;
89impl<'a, REG> ModeW<'a, REG>
90where
91    REG: crate::Writable + crate::RegisterSpec,
92    REG::Ux: From<u8>,
93{
94    #[doc = "USART mode with external clock"]
95    #[inline(always)]
96    pub fn usart_ext_clk(self) -> &'a mut crate::W<REG> {
97        self.variant(Modeselect::UsartExtClk)
98    }
99    #[doc = "USART mode with internal clock"]
100    #[inline(always)]
101    pub fn usart_int_clk(self) -> &'a mut crate::W<REG> {
102        self.variant(Modeselect::UsartIntClk)
103    }
104    #[doc = "SPI mode with external clock"]
105    #[inline(always)]
106    pub fn spi_slave(self) -> &'a mut crate::W<REG> {
107        self.variant(Modeselect::SpiSlave)
108    }
109    #[doc = "SPI mode with internal clock"]
110    #[inline(always)]
111    pub fn spi_master(self) -> &'a mut crate::W<REG> {
112        self.variant(Modeselect::SpiMaster)
113    }
114    #[doc = "I2C mode with external clock"]
115    #[inline(always)]
116    pub fn i2c_slave(self) -> &'a mut crate::W<REG> {
117        self.variant(Modeselect::I2cSlave)
118    }
119    #[doc = "I2C mode with internal clock"]
120    #[inline(always)]
121    pub fn i2c_master(self) -> &'a mut crate::W<REG> {
122        self.variant(Modeselect::I2cMaster)
123    }
124}
125#[doc = "Field `RUNSTDBY` reader - Run during Standby"]
126pub type RunstdbyR = crate::BitReader;
127#[doc = "Field `RUNSTDBY` writer - Run during Standby"]
128pub type RunstdbyW<'a, REG> = crate::BitWriter<'a, REG>;
129#[doc = "Field `IBON` reader - Immediate Buffer Overflow Notification"]
130pub type IbonR = crate::BitReader;
131#[doc = "Field `IBON` writer - Immediate Buffer Overflow Notification"]
132pub type IbonW<'a, REG> = crate::BitWriter<'a, REG>;
133#[doc = "Field `SAMPR` reader - Sample"]
134pub type SamprR = crate::FieldReader;
135#[doc = "Field `SAMPR` writer - Sample"]
136pub type SamprW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
137#[doc = "Field `TXPO` reader - Transmit Data Pinout"]
138pub type TxpoR = crate::FieldReader;
139#[doc = "Field `TXPO` writer - Transmit Data Pinout"]
140pub type TxpoW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
141#[doc = "Field `RXPO` reader - Receive Data Pinout"]
142pub type RxpoR = crate::FieldReader;
143#[doc = "Field `RXPO` writer - Receive Data Pinout"]
144pub type RxpoW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
145#[doc = "Field `SAMPA` reader - Sample Adjustment"]
146pub type SampaR = crate::FieldReader;
147#[doc = "Field `SAMPA` writer - Sample Adjustment"]
148pub type SampaW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
149#[doc = "Field `FORM` reader - Frame Format"]
150pub type FormR = crate::FieldReader;
151#[doc = "Field `FORM` writer - Frame Format"]
152pub type FormW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
153#[doc = "Field `CMODE` reader - Communication Mode"]
154pub type CmodeR = crate::BitReader;
155#[doc = "Field `CMODE` writer - Communication Mode"]
156pub type CmodeW<'a, REG> = crate::BitWriter<'a, REG>;
157#[doc = "Field `CPOL` reader - Clock Polarity"]
158pub type CpolR = crate::BitReader;
159#[doc = "Field `CPOL` writer - Clock Polarity"]
160pub type CpolW<'a, REG> = crate::BitWriter<'a, REG>;
161#[doc = "Field `DORD` reader - Data Order"]
162pub type DordR = crate::BitReader;
163#[doc = "Field `DORD` writer - Data Order"]
164pub type DordW<'a, REG> = crate::BitWriter<'a, REG>;
165impl R {
166    #[doc = "Bit 0 - Software Reset"]
167    #[inline(always)]
168    pub fn swrst(&self) -> SwrstR {
169        SwrstR::new((self.bits & 1) != 0)
170    }
171    #[doc = "Bit 1 - Enable"]
172    #[inline(always)]
173    pub fn enable(&self) -> EnableR {
174        EnableR::new(((self.bits >> 1) & 1) != 0)
175    }
176    #[doc = "Bits 2:4 - Operating Mode"]
177    #[inline(always)]
178    pub fn mode(&self) -> ModeR {
179        ModeR::new(((self.bits >> 2) & 7) as u8)
180    }
181    #[doc = "Bit 7 - Run during Standby"]
182    #[inline(always)]
183    pub fn runstdby(&self) -> RunstdbyR {
184        RunstdbyR::new(((self.bits >> 7) & 1) != 0)
185    }
186    #[doc = "Bit 8 - Immediate Buffer Overflow Notification"]
187    #[inline(always)]
188    pub fn ibon(&self) -> IbonR {
189        IbonR::new(((self.bits >> 8) & 1) != 0)
190    }
191    #[doc = "Bits 13:15 - Sample"]
192    #[inline(always)]
193    pub fn sampr(&self) -> SamprR {
194        SamprR::new(((self.bits >> 13) & 7) as u8)
195    }
196    #[doc = "Bits 16:17 - Transmit Data Pinout"]
197    #[inline(always)]
198    pub fn txpo(&self) -> TxpoR {
199        TxpoR::new(((self.bits >> 16) & 3) as u8)
200    }
201    #[doc = "Bits 20:21 - Receive Data Pinout"]
202    #[inline(always)]
203    pub fn rxpo(&self) -> RxpoR {
204        RxpoR::new(((self.bits >> 20) & 3) as u8)
205    }
206    #[doc = "Bits 22:23 - Sample Adjustment"]
207    #[inline(always)]
208    pub fn sampa(&self) -> SampaR {
209        SampaR::new(((self.bits >> 22) & 3) as u8)
210    }
211    #[doc = "Bits 24:27 - Frame Format"]
212    #[inline(always)]
213    pub fn form(&self) -> FormR {
214        FormR::new(((self.bits >> 24) & 0x0f) as u8)
215    }
216    #[doc = "Bit 28 - Communication Mode"]
217    #[inline(always)]
218    pub fn cmode(&self) -> CmodeR {
219        CmodeR::new(((self.bits >> 28) & 1) != 0)
220    }
221    #[doc = "Bit 29 - Clock Polarity"]
222    #[inline(always)]
223    pub fn cpol(&self) -> CpolR {
224        CpolR::new(((self.bits >> 29) & 1) != 0)
225    }
226    #[doc = "Bit 30 - Data Order"]
227    #[inline(always)]
228    pub fn dord(&self) -> DordR {
229        DordR::new(((self.bits >> 30) & 1) != 0)
230    }
231}
232impl W {
233    #[doc = "Bit 0 - Software Reset"]
234    #[inline(always)]
235    #[must_use]
236    pub fn swrst(&mut self) -> SwrstW<CtrlaSpec> {
237        SwrstW::new(self, 0)
238    }
239    #[doc = "Bit 1 - Enable"]
240    #[inline(always)]
241    #[must_use]
242    pub fn enable(&mut self) -> EnableW<CtrlaSpec> {
243        EnableW::new(self, 1)
244    }
245    #[doc = "Bits 2:4 - Operating Mode"]
246    #[inline(always)]
247    #[must_use]
248    pub fn mode(&mut self) -> ModeW<CtrlaSpec> {
249        ModeW::new(self, 2)
250    }
251    #[doc = "Bit 7 - Run during Standby"]
252    #[inline(always)]
253    #[must_use]
254    pub fn runstdby(&mut self) -> RunstdbyW<CtrlaSpec> {
255        RunstdbyW::new(self, 7)
256    }
257    #[doc = "Bit 8 - Immediate Buffer Overflow Notification"]
258    #[inline(always)]
259    #[must_use]
260    pub fn ibon(&mut self) -> IbonW<CtrlaSpec> {
261        IbonW::new(self, 8)
262    }
263    #[doc = "Bits 13:15 - Sample"]
264    #[inline(always)]
265    #[must_use]
266    pub fn sampr(&mut self) -> SamprW<CtrlaSpec> {
267        SamprW::new(self, 13)
268    }
269    #[doc = "Bits 16:17 - Transmit Data Pinout"]
270    #[inline(always)]
271    #[must_use]
272    pub fn txpo(&mut self) -> TxpoW<CtrlaSpec> {
273        TxpoW::new(self, 16)
274    }
275    #[doc = "Bits 20:21 - Receive Data Pinout"]
276    #[inline(always)]
277    #[must_use]
278    pub fn rxpo(&mut self) -> RxpoW<CtrlaSpec> {
279        RxpoW::new(self, 20)
280    }
281    #[doc = "Bits 22:23 - Sample Adjustment"]
282    #[inline(always)]
283    #[must_use]
284    pub fn sampa(&mut self) -> SampaW<CtrlaSpec> {
285        SampaW::new(self, 22)
286    }
287    #[doc = "Bits 24:27 - Frame Format"]
288    #[inline(always)]
289    #[must_use]
290    pub fn form(&mut self) -> FormW<CtrlaSpec> {
291        FormW::new(self, 24)
292    }
293    #[doc = "Bit 28 - Communication Mode"]
294    #[inline(always)]
295    #[must_use]
296    pub fn cmode(&mut self) -> CmodeW<CtrlaSpec> {
297        CmodeW::new(self, 28)
298    }
299    #[doc = "Bit 29 - Clock Polarity"]
300    #[inline(always)]
301    #[must_use]
302    pub fn cpol(&mut self) -> CpolW<CtrlaSpec> {
303        CpolW::new(self, 29)
304    }
305    #[doc = "Bit 30 - Data Order"]
306    #[inline(always)]
307    #[must_use]
308    pub fn dord(&mut self) -> DordW<CtrlaSpec> {
309        DordW::new(self, 30)
310    }
311}
312#[doc = "USART Control A\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrla::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrla::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
313pub struct CtrlaSpec;
314impl crate::RegisterSpec for CtrlaSpec {
315    type Ux = u32;
316}
317#[doc = "`read()` method returns [`ctrla::R`](R) reader structure"]
318impl crate::Readable for CtrlaSpec {}
319#[doc = "`write(|w| ..)` method takes [`ctrla::W`](W) writer structure"]
320impl crate::Writable for CtrlaSpec {
321    type Safety = crate::Unsafe;
322    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
323    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
324}
325#[doc = "`reset()` method sets CTRLA to value 0"]
326impl crate::Resettable for CtrlaSpec {
327    const RESET_VALUE: u32 = 0;
328}
atsamd11c/sercom0/usart/ctrla.rs

atsamd11c/sercom0/usart/
ctrla.rs
