atsamd51n/sercom0/
spis.rs

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1#[repr(C)]
2#[doc = "SPI Slave Mode"]
3#[doc(alias = "SPIS")]
4pub struct Spis {
5    ctrla: Ctrla,
6    ctrlb: Ctrlb,
7    ctrlc: Ctrlc,
8    baud: Baud,
9    _reserved4: [u8; 0x07],
10    intenclr: Intenclr,
11    _reserved5: [u8; 0x01],
12    intenset: Intenset,
13    _reserved6: [u8; 0x01],
14    intflag: Intflag,
15    _reserved7: [u8; 0x01],
16    status: Status,
17    syncbusy: Syncbusy,
18    _reserved9: [u8; 0x02],
19    length: Length,
20    addr: Addr,
21    data: Data,
22    _reserved12: [u8; 0x04],
23    dbgctrl: Dbgctrl,
24}
25impl Spis {
26    #[doc = "0x00 - SPIS Control A"]
27    #[inline(always)]
28    pub const fn ctrla(&self) -> &Ctrla {
29        &self.ctrla
30    }
31    #[doc = "0x04 - SPIS Control B"]
32    #[inline(always)]
33    pub const fn ctrlb(&self) -> &Ctrlb {
34        &self.ctrlb
35    }
36    #[doc = "0x08 - SPIS Control C"]
37    #[inline(always)]
38    pub const fn ctrlc(&self) -> &Ctrlc {
39        &self.ctrlc
40    }
41    #[doc = "0x0c - SPIS Baud Rate"]
42    #[inline(always)]
43    pub const fn baud(&self) -> &Baud {
44        &self.baud
45    }
46    #[doc = "0x14 - SPIS Interrupt Enable Clear"]
47    #[inline(always)]
48    pub const fn intenclr(&self) -> &Intenclr {
49        &self.intenclr
50    }
51    #[doc = "0x16 - SPIS Interrupt Enable Set"]
52    #[inline(always)]
53    pub const fn intenset(&self) -> &Intenset {
54        &self.intenset
55    }
56    #[doc = "0x18 - SPIS Interrupt Flag Status and Clear"]
57    #[inline(always)]
58    pub const fn intflag(&self) -> &Intflag {
59        &self.intflag
60    }
61    #[doc = "0x1a - SPIS Status"]
62    #[inline(always)]
63    pub const fn status(&self) -> &Status {
64        &self.status
65    }
66    #[doc = "0x1c - SPIS Synchronization Busy"]
67    #[inline(always)]
68    pub const fn syncbusy(&self) -> &Syncbusy {
69        &self.syncbusy
70    }
71    #[doc = "0x22 - SPIS Length"]
72    #[inline(always)]
73    pub const fn length(&self) -> &Length {
74        &self.length
75    }
76    #[doc = "0x24 - SPIS Address"]
77    #[inline(always)]
78    pub const fn addr(&self) -> &Addr {
79        &self.addr
80    }
81    #[doc = "0x28 - SPIS Data"]
82    #[inline(always)]
83    pub const fn data(&self) -> &Data {
84        &self.data
85    }
86    #[doc = "0x30 - SPIS Debug Control"]
87    #[inline(always)]
88    pub const fn dbgctrl(&self) -> &Dbgctrl {
89        &self.dbgctrl
90    }
91}
92#[doc = "CTRLA (rw) register accessor: SPIS Control A\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrla::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrla::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrla`]
93module"]
94#[doc(alias = "CTRLA")]
95pub type Ctrla = crate::Reg<ctrla::CtrlaSpec>;
96#[doc = "SPIS Control A"]
97pub mod ctrla;
98#[doc = "CTRLB (rw) register accessor: SPIS Control B\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrlb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrlb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrlb`]
99module"]
100#[doc(alias = "CTRLB")]
101pub type Ctrlb = crate::Reg<ctrlb::CtrlbSpec>;
102#[doc = "SPIS Control B"]
103pub mod ctrlb;
104#[doc = "CTRLC (rw) register accessor: SPIS Control C\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrlc::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrlc::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrlc`]
105module"]
106#[doc(alias = "CTRLC")]
107pub type Ctrlc = crate::Reg<ctrlc::CtrlcSpec>;
108#[doc = "SPIS Control C"]
109pub mod ctrlc;
110#[doc = "BAUD (rw) register accessor: SPIS Baud Rate\n\nYou can [`read`](crate::Reg::read) this register and get [`baud::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`baud::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@baud`]
111module"]
112#[doc(alias = "BAUD")]
113pub type Baud = crate::Reg<baud::BaudSpec>;
114#[doc = "SPIS Baud Rate"]
115pub mod baud;
116#[doc = "INTENCLR (rw) register accessor: SPIS Interrupt Enable Clear\n\nYou can [`read`](crate::Reg::read) this register and get [`intenclr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intenclr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intenclr`]
117module"]
118#[doc(alias = "INTENCLR")]
119pub type Intenclr = crate::Reg<intenclr::IntenclrSpec>;
120#[doc = "SPIS Interrupt Enable Clear"]
121pub mod intenclr;
122#[doc = "INTENSET (rw) register accessor: SPIS Interrupt Enable Set\n\nYou can [`read`](crate::Reg::read) this register and get [`intenset::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intenset::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intenset`]
123module"]
124#[doc(alias = "INTENSET")]
125pub type Intenset = crate::Reg<intenset::IntensetSpec>;
126#[doc = "SPIS Interrupt Enable Set"]
127pub mod intenset;
128#[doc = "INTFLAG (rw) register accessor: SPIS Interrupt Flag Status and Clear\n\nYou can [`read`](crate::Reg::read) this register and get [`intflag::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intflag::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intflag`]
129module"]
130#[doc(alias = "INTFLAG")]
131pub type Intflag = crate::Reg<intflag::IntflagSpec>;
132#[doc = "SPIS Interrupt Flag Status and Clear"]
133pub mod intflag;
134#[doc = "STATUS (rw) register accessor: SPIS Status\n\nYou can [`read`](crate::Reg::read) this register and get [`status::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`status::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@status`]
135module"]
136#[doc(alias = "STATUS")]
137pub type Status = crate::Reg<status::StatusSpec>;
138#[doc = "SPIS Status"]
139pub mod status;
140#[doc = "SYNCBUSY (r) register accessor: SPIS Synchronization Busy\n\nYou can [`read`](crate::Reg::read) this register and get [`syncbusy::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@syncbusy`]
141module"]
142#[doc(alias = "SYNCBUSY")]
143pub type Syncbusy = crate::Reg<syncbusy::SyncbusySpec>;
144#[doc = "SPIS Synchronization Busy"]
145pub mod syncbusy;
146#[doc = "LENGTH (rw) register accessor: SPIS Length\n\nYou can [`read`](crate::Reg::read) this register and get [`length::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`length::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@length`]
147module"]
148#[doc(alias = "LENGTH")]
149pub type Length = crate::Reg<length::LengthSpec>;
150#[doc = "SPIS Length"]
151pub mod length;
152#[doc = "ADDR (rw) register accessor: SPIS Address\n\nYou can [`read`](crate::Reg::read) this register and get [`addr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`addr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@addr`]
153module"]
154#[doc(alias = "ADDR")]
155pub type Addr = crate::Reg<addr::AddrSpec>;
156#[doc = "SPIS Address"]
157pub mod addr;
158#[doc = "DATA (rw) register accessor: SPIS Data\n\nYou can [`read`](crate::Reg::read) this register and get [`data::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data`]
159module"]
160#[doc(alias = "DATA")]
161pub type Data = crate::Reg<data::DataSpec>;
162#[doc = "SPIS Data"]
163pub mod data;
164#[doc = "DBGCTRL (rw) register accessor: SPIS Debug Control\n\nYou can [`read`](crate::Reg::read) this register and get [`dbgctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dbgctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dbgctrl`]
165module"]
166#[doc(alias = "DBGCTRL")]
167pub type Dbgctrl = crate::Reg<dbgctrl::DbgctrlSpec>;
168#[doc = "SPIS Debug Control"]
169pub mod dbgctrl;
atsamd51n/sercom0/spis.rs

atsamd51n/sercom0/
spis.rs
