1#[repr(C)]
2#[doc = "USB is Host"]
3#[doc(alias = "HOST")]
4pub struct Host {
5 ctrla: Ctrla,
6 _reserved1: [u8; 0x01],
7 syncbusy: Syncbusy,
8 qosctrl: Qosctrl,
9 _reserved3: [u8; 0x04],
10 ctrlb: Ctrlb,
11 hsofc: Hsofc,
12 _reserved5: [u8; 0x01],
13 status: Status,
14 fsmstatus: Fsmstatus,
15 _reserved7: [u8; 0x02],
16 fnum: Fnum,
17 flenhigh: Flenhigh,
18 _reserved9: [u8; 0x01],
19 intenclr: Intenclr,
20 _reserved10: [u8; 0x02],
21 intenset: Intenset,
22 _reserved11: [u8; 0x02],
23 intflag: Intflag,
24 _reserved12: [u8; 0x02],
25 pintsmry: Pintsmry,
26 _reserved13: [u8; 0x02],
27 descadd: Descadd,
28 padcal: Padcal,
29 _reserved15: [u8; 0xd6],
30 host_pipe: (),
31}
32impl Host {
33#[doc = "0x00 - Control A"]
34 #[inline(always)]
35pub const fn ctrla(&self) -> &Ctrla {
36&self.ctrla
37 }
38#[doc = "0x02 - Synchronization Busy"]
39 #[inline(always)]
40pub const fn syncbusy(&self) -> &Syncbusy {
41&self.syncbusy
42 }
43#[doc = "0x03 - USB Quality Of Service"]
44 #[inline(always)]
45pub const fn qosctrl(&self) -> &Qosctrl {
46&self.qosctrl
47 }
48#[doc = "0x08 - HOST Control B"]
49 #[inline(always)]
50pub const fn ctrlb(&self) -> &Ctrlb {
51&self.ctrlb
52 }
53#[doc = "0x0a - HOST Host Start Of Frame Control"]
54 #[inline(always)]
55pub const fn hsofc(&self) -> &Hsofc {
56&self.hsofc
57 }
58#[doc = "0x0c - HOST Status"]
59 #[inline(always)]
60pub const fn status(&self) -> &Status {
61&self.status
62 }
63#[doc = "0x0d - Finite State Machine Status"]
64 #[inline(always)]
65pub const fn fsmstatus(&self) -> &Fsmstatus {
66&self.fsmstatus
67 }
68#[doc = "0x10 - HOST Host Frame Number"]
69 #[inline(always)]
70pub const fn fnum(&self) -> &Fnum {
71&self.fnum
72 }
73#[doc = "0x12 - HOST Host Frame Length"]
74 #[inline(always)]
75pub const fn flenhigh(&self) -> &Flenhigh {
76&self.flenhigh
77 }
78#[doc = "0x14 - HOST Host Interrupt Enable Clear"]
79 #[inline(always)]
80pub const fn intenclr(&self) -> &Intenclr {
81&self.intenclr
82 }
83#[doc = "0x18 - HOST Host Interrupt Enable Set"]
84 #[inline(always)]
85pub const fn intenset(&self) -> &Intenset {
86&self.intenset
87 }
88#[doc = "0x1c - HOST Host Interrupt Flag"]
89 #[inline(always)]
90pub const fn intflag(&self) -> &Intflag {
91&self.intflag
92 }
93#[doc = "0x20 - HOST Pipe Interrupt Summary"]
94 #[inline(always)]
95pub const fn pintsmry(&self) -> &Pintsmry {
96&self.pintsmry
97 }
98#[doc = "0x24 - Descriptor Address"]
99 #[inline(always)]
100pub const fn descadd(&self) -> &Descadd {
101&self.descadd
102 }
103#[doc = "0x28 - USB PAD Calibration"]
104 #[inline(always)]
105pub const fn padcal(&self) -> &Padcal {
106&self.padcal
107 }
108#[doc = "0x100..0x150 - HOST_PIPE\\[%s\\]"]
109 #[inline(always)]
110pub const fn host_pipe(&self, n: usize) -> &HostPipe {
111#[allow(clippy::no_effect)]
112[(); 8][n];
113unsafe {
114&*(self as *const Self)
115 .cast::<u8>()
116 .add(256)
117 .add(32 * n)
118 .cast()
119 }
120 }
121#[doc = "Iterator for array of:"]
122 #[doc = "0x100..0x150 - HOST_PIPE\\[%s\\]"]
123 #[inline(always)]
124pub fn host_pipe_iter(&self) -> impl Iterator<Item = &HostPipe> {
125 (0..8).map(move |n| unsafe {
126&*(self as *const Self)
127 .cast::<u8>()
128 .add(256)
129 .add(32 * n)
130 .cast()
131 })
132 }
133}
134#[doc = "CTRLA (rw) register accessor: Control A\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrla::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrla::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrla`]
135module"]
136#[doc(alias = "CTRLA")]
137pub type Ctrla = crate::Reg<ctrla::CtrlaSpec>;
138#[doc = "Control A"]
139pub mod ctrla;
140#[doc = "SYNCBUSY (r) register accessor: Synchronization Busy\n\nYou can [`read`](crate::Reg::read) this register and get [`syncbusy::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@syncbusy`]
141module"]
142#[doc(alias = "SYNCBUSY")]
143pub type Syncbusy = crate::Reg<syncbusy::SyncbusySpec>;
144#[doc = "Synchronization Busy"]
145pub mod syncbusy;
146#[doc = "QOSCTRL (rw) register accessor: USB Quality Of Service\n\nYou can [`read`](crate::Reg::read) this register and get [`qosctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qosctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qosctrl`]
147module"]
148#[doc(alias = "QOSCTRL")]
149pub type Qosctrl = crate::Reg<qosctrl::QosctrlSpec>;
150#[doc = "USB Quality Of Service"]
151pub mod qosctrl;
152#[doc = "CTRLB (rw) register accessor: HOST Control B\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrlb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrlb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrlb`]
153module"]
154#[doc(alias = "CTRLB")]
155pub type Ctrlb = crate::Reg<ctrlb::CtrlbSpec>;
156#[doc = "HOST Control B"]
157pub mod ctrlb;
158#[doc = "HSOFC (rw) register accessor: HOST Host Start Of Frame Control\n\nYou can [`read`](crate::Reg::read) this register and get [`hsofc::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hsofc::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hsofc`]
159module"]
160#[doc(alias = "HSOFC")]
161pub type Hsofc = crate::Reg<hsofc::HsofcSpec>;
162#[doc = "HOST Host Start Of Frame Control"]
163pub mod hsofc;
164#[doc = "STATUS (rw) register accessor: HOST Status\n\nYou can [`read`](crate::Reg::read) this register and get [`status::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`status::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@status`]
165module"]
166#[doc(alias = "STATUS")]
167pub type Status = crate::Reg<status::StatusSpec>;
168#[doc = "HOST Status"]
169pub mod status;
170#[doc = "FSMSTATUS (r) register accessor: Finite State Machine Status\n\nYou can [`read`](crate::Reg::read) this register and get [`fsmstatus::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fsmstatus`]
171module"]
172#[doc(alias = "FSMSTATUS")]
173pub type Fsmstatus = crate::Reg<fsmstatus::FsmstatusSpec>;
174#[doc = "Finite State Machine Status"]
175pub mod fsmstatus;
176#[doc = "FNUM (rw) register accessor: HOST Host Frame Number\n\nYou can [`read`](crate::Reg::read) this register and get [`fnum::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fnum::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fnum`]
177module"]
178#[doc(alias = "FNUM")]
179pub type Fnum = crate::Reg<fnum::FnumSpec>;
180#[doc = "HOST Host Frame Number"]
181pub mod fnum;
182#[doc = "FLENHIGH (r) register accessor: HOST Host Frame Length\n\nYou can [`read`](crate::Reg::read) this register and get [`flenhigh::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@flenhigh`]
183module"]
184#[doc(alias = "FLENHIGH")]
185pub type Flenhigh = crate::Reg<flenhigh::FlenhighSpec>;
186#[doc = "HOST Host Frame Length"]
187pub mod flenhigh;
188#[doc = "INTENCLR (rw) register accessor: HOST Host Interrupt Enable Clear\n\nYou can [`read`](crate::Reg::read) this register and get [`intenclr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intenclr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intenclr`]
189module"]
190#[doc(alias = "INTENCLR")]
191pub type Intenclr = crate::Reg<intenclr::IntenclrSpec>;
192#[doc = "HOST Host Interrupt Enable Clear"]
193pub mod intenclr;
194#[doc = "INTENSET (rw) register accessor: HOST Host Interrupt Enable Set\n\nYou can [`read`](crate::Reg::read) this register and get [`intenset::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intenset::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intenset`]
195module"]
196#[doc(alias = "INTENSET")]
197pub type Intenset = crate::Reg<intenset::IntensetSpec>;
198#[doc = "HOST Host Interrupt Enable Set"]
199pub mod intenset;
200#[doc = "INTFLAG (rw) register accessor: HOST Host Interrupt Flag\n\nYou can [`read`](crate::Reg::read) this register and get [`intflag::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intflag::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intflag`]
201module"]
202#[doc(alias = "INTFLAG")]
203pub type Intflag = crate::Reg<intflag::IntflagSpec>;
204#[doc = "HOST Host Interrupt Flag"]
205pub mod intflag;
206#[doc = "PINTSMRY (r) register accessor: HOST Pipe Interrupt Summary\n\nYou can [`read`](crate::Reg::read) this register and get [`pintsmry::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pintsmry`]
207module"]
208#[doc(alias = "PINTSMRY")]
209pub type Pintsmry = crate::Reg<pintsmry::PintsmrySpec>;
210#[doc = "HOST Pipe Interrupt Summary"]
211pub mod pintsmry;
212#[doc = "DESCADD (rw) register accessor: Descriptor Address\n\nYou can [`read`](crate::Reg::read) this register and get [`descadd::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`descadd::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@descadd`]
213module"]
214#[doc(alias = "DESCADD")]
215pub type Descadd = crate::Reg<descadd::DescaddSpec>;
216#[doc = "Descriptor Address"]
217pub mod descadd;
218#[doc = "PADCAL (rw) register accessor: USB PAD Calibration\n\nYou can [`read`](crate::Reg::read) this register and get [`padcal::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`padcal::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcal`]
219module"]
220#[doc(alias = "PADCAL")]
221pub type Padcal = crate::Reg<padcal::PadcalSpec>;
222#[doc = "USB PAD Calibration"]
223pub mod padcal;
224#[doc = "HOST_PIPE\\[%s\\]"]
225pub use self::host_pipe::HostPipe;
226#[doc = r"Cluster"]
227#[doc = "HOST_PIPE\\[%s\\]"]
228pub mod host_pipe;