atsamd51n/mclk/
hsdiv.rs

1#[doc = "Register `HSDIV` reader"]
2pub type R = crate::R<HsdivSpec>;
3#[doc = "CPU Clock Division Factor\n\nValue on reset: 1"]
4#[derive(Clone, Copy, Debug, PartialEq, Eq)]
5#[repr(u8)]
6pub enum Divselect {
7    #[doc = "1: Divide by 1"]
8    Div1 = 1,
9}
10impl From<Divselect> for u8 {
11    #[inline(always)]
12    fn from(variant: Divselect) -> Self {
13        variant as _
14    }
15}
16impl crate::FieldSpec for Divselect {
17    type Ux = u8;
18}
19impl crate::IsEnum for Divselect {}
20#[doc = "Field `DIV` reader - CPU Clock Division Factor"]
21pub type DivR = crate::FieldReader<Divselect>;
22impl DivR {
23    #[doc = "Get enumerated values variant"]
24    #[inline(always)]
25    pub const fn variant(&self) -> Option<Divselect> {
26        match self.bits {
27            1 => Some(Divselect::Div1),
28            _ => None,
29        }
30    }
31    #[doc = "Divide by 1"]
32    #[inline(always)]
33    pub fn is_div1(&self) -> bool {
34        *self == Divselect::Div1
35    }
36}
37impl R {
38    #[doc = "Bits 0:7 - CPU Clock Division Factor"]
39    #[inline(always)]
40    pub fn div(&self) -> DivR {
41        DivR::new(self.bits)
42    }
43}
44#[doc = "HS Clock Division\n\nYou can [`read`](crate::Reg::read) this register and get [`hsdiv::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
45pub struct HsdivSpec;
46impl crate::RegisterSpec for HsdivSpec {
47    type Ux = u8;
48}
49#[doc = "`read()` method returns [`hsdiv::R`](R) reader structure"]
50impl crate::Readable for HsdivSpec {}
51#[doc = "`reset()` method sets HSDIV to value 0x01"]
52impl crate::Resettable for HsdivSpec {
53    const RESET_VALUE: u8 = 0x01;
54}
atsamd51n/mclk/hsdiv.rs

atsamd51n/mclk/
hsdiv.rs
