atsamd51n/osc32kctrl/
xosc32k.rs

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1#[doc = "Register `XOSC32K` reader"]
2pub type R = crate::R<Xosc32kSpec>;
3#[doc = "Register `XOSC32K` writer"]
4pub type W = crate::W<Xosc32kSpec>;
5#[doc = "Field `ENABLE` reader - Oscillator Enable"]
6pub type EnableR = crate::BitReader;
7#[doc = "Field `ENABLE` writer - Oscillator Enable"]
8pub type EnableW<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `XTALEN` reader - Crystal Oscillator Enable"]
10pub type XtalenR = crate::BitReader;
11#[doc = "Field `XTALEN` writer - Crystal Oscillator Enable"]
12pub type XtalenW<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `EN32K` reader - 32kHz Output Enable"]
14pub type En32kR = crate::BitReader;
15#[doc = "Field `EN32K` writer - 32kHz Output Enable"]
16pub type En32kW<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `EN1K` reader - 1kHz Output Enable"]
18pub type En1kR = crate::BitReader;
19#[doc = "Field `EN1K` writer - 1kHz Output Enable"]
20pub type En1kW<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `RUNSTDBY` reader - Run in Standby"]
22pub type RunstdbyR = crate::BitReader;
23#[doc = "Field `RUNSTDBY` writer - Run in Standby"]
24pub type RunstdbyW<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `ONDEMAND` reader - On Demand Control"]
26pub type OndemandR = crate::BitReader;
27#[doc = "Field `ONDEMAND` writer - On Demand Control"]
28pub type OndemandW<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Oscillator Start-Up Time\n\nValue on reset: 0"]
30#[derive(Clone, Copy, Debug, PartialEq, Eq)]
31#[repr(u8)]
32pub enum Startupselect {
33    #[doc = "0: 62.6 ms"]
34    Cycle2048 = 0,
35    #[doc = "1: 125 ms"]
36    Cycle4096 = 1,
37    #[doc = "2: 500 ms"]
38    Cycle16384 = 2,
39    #[doc = "3: 1000 ms"]
40    Cycle32768 = 3,
41    #[doc = "4: 2000 ms"]
42    Cycle65536 = 4,
43    #[doc = "5: 4000 ms"]
44    Cycle131072 = 5,
45    #[doc = "6: 8000 ms"]
46    Cycle262144 = 6,
47}
48impl From<Startupselect> for u8 {
49    #[inline(always)]
50    fn from(variant: Startupselect) -> Self {
51        variant as _
52    }
53}
54impl crate::FieldSpec for Startupselect {
55    type Ux = u8;
56}
57impl crate::IsEnum for Startupselect {}
58#[doc = "Field `STARTUP` reader - Oscillator Start-Up Time"]
59pub type StartupR = crate::FieldReader<Startupselect>;
60impl StartupR {
61    #[doc = "Get enumerated values variant"]
62    #[inline(always)]
63    pub const fn variant(&self) -> Option<Startupselect> {
64        match self.bits {
65            0 => Some(Startupselect::Cycle2048),
66            1 => Some(Startupselect::Cycle4096),
67            2 => Some(Startupselect::Cycle16384),
68            3 => Some(Startupselect::Cycle32768),
69            4 => Some(Startupselect::Cycle65536),
70            5 => Some(Startupselect::Cycle131072),
71            6 => Some(Startupselect::Cycle262144),
72            _ => None,
73        }
74    }
75    #[doc = "62.6 ms"]
76    #[inline(always)]
77    pub fn is_cycle2048(&self) -> bool {
78        *self == Startupselect::Cycle2048
79    }
80    #[doc = "125 ms"]
81    #[inline(always)]
82    pub fn is_cycle4096(&self) -> bool {
83        *self == Startupselect::Cycle4096
84    }
85    #[doc = "500 ms"]
86    #[inline(always)]
87    pub fn is_cycle16384(&self) -> bool {
88        *self == Startupselect::Cycle16384
89    }
90    #[doc = "1000 ms"]
91    #[inline(always)]
92    pub fn is_cycle32768(&self) -> bool {
93        *self == Startupselect::Cycle32768
94    }
95    #[doc = "2000 ms"]
96    #[inline(always)]
97    pub fn is_cycle65536(&self) -> bool {
98        *self == Startupselect::Cycle65536
99    }
100    #[doc = "4000 ms"]
101    #[inline(always)]
102    pub fn is_cycle131072(&self) -> bool {
103        *self == Startupselect::Cycle131072
104    }
105    #[doc = "8000 ms"]
106    #[inline(always)]
107    pub fn is_cycle262144(&self) -> bool {
108        *self == Startupselect::Cycle262144
109    }
110}
111#[doc = "Field `STARTUP` writer - Oscillator Start-Up Time"]
112pub type StartupW<'a, REG> = crate::FieldWriter<'a, REG, 3, Startupselect>;
113impl<'a, REG> StartupW<'a, REG>
114where
115    REG: crate::Writable + crate::RegisterSpec,
116    REG::Ux: From<u8>,
117{
118    #[doc = "62.6 ms"]
119    #[inline(always)]
120    pub fn cycle2048(self) -> &'a mut crate::W<REG> {
121        self.variant(Startupselect::Cycle2048)
122    }
123    #[doc = "125 ms"]
124    #[inline(always)]
125    pub fn cycle4096(self) -> &'a mut crate::W<REG> {
126        self.variant(Startupselect::Cycle4096)
127    }
128    #[doc = "500 ms"]
129    #[inline(always)]
130    pub fn cycle16384(self) -> &'a mut crate::W<REG> {
131        self.variant(Startupselect::Cycle16384)
132    }
133    #[doc = "1000 ms"]
134    #[inline(always)]
135    pub fn cycle32768(self) -> &'a mut crate::W<REG> {
136        self.variant(Startupselect::Cycle32768)
137    }
138    #[doc = "2000 ms"]
139    #[inline(always)]
140    pub fn cycle65536(self) -> &'a mut crate::W<REG> {
141        self.variant(Startupselect::Cycle65536)
142    }
143    #[doc = "4000 ms"]
144    #[inline(always)]
145    pub fn cycle131072(self) -> &'a mut crate::W<REG> {
146        self.variant(Startupselect::Cycle131072)
147    }
148    #[doc = "8000 ms"]
149    #[inline(always)]
150    pub fn cycle262144(self) -> &'a mut crate::W<REG> {
151        self.variant(Startupselect::Cycle262144)
152    }
153}
154#[doc = "Field `WRTLOCK` reader - Write Lock"]
155pub type WrtlockR = crate::BitReader;
156#[doc = "Field `WRTLOCK` writer - Write Lock"]
157pub type WrtlockW<'a, REG> = crate::BitWriter<'a, REG>;
158#[doc = "Control Gain Mode\n\nValue on reset: 1"]
159#[derive(Clone, Copy, Debug, PartialEq, Eq)]
160#[repr(u8)]
161pub enum Cgmselect {
162    #[doc = "1: Standard mode"]
163    Xt = 1,
164    #[doc = "2: High Speed mode"]
165    Hs = 2,
166}
167impl From<Cgmselect> for u8 {
168    #[inline(always)]
169    fn from(variant: Cgmselect) -> Self {
170        variant as _
171    }
172}
173impl crate::FieldSpec for Cgmselect {
174    type Ux = u8;
175}
176impl crate::IsEnum for Cgmselect {}
177#[doc = "Field `CGM` reader - Control Gain Mode"]
178pub type CgmR = crate::FieldReader<Cgmselect>;
179impl CgmR {
180    #[doc = "Get enumerated values variant"]
181    #[inline(always)]
182    pub const fn variant(&self) -> Option<Cgmselect> {
183        match self.bits {
184            1 => Some(Cgmselect::Xt),
185            2 => Some(Cgmselect::Hs),
186            _ => None,
187        }
188    }
189    #[doc = "Standard mode"]
190    #[inline(always)]
191    pub fn is_xt(&self) -> bool {
192        *self == Cgmselect::Xt
193    }
194    #[doc = "High Speed mode"]
195    #[inline(always)]
196    pub fn is_hs(&self) -> bool {
197        *self == Cgmselect::Hs
198    }
199}
200#[doc = "Field `CGM` writer - Control Gain Mode"]
201pub type CgmW<'a, REG> = crate::FieldWriter<'a, REG, 2, Cgmselect>;
202impl<'a, REG> CgmW<'a, REG>
203where
204    REG: crate::Writable + crate::RegisterSpec,
205    REG::Ux: From<u8>,
206{
207    #[doc = "Standard mode"]
208    #[inline(always)]
209    pub fn xt(self) -> &'a mut crate::W<REG> {
210        self.variant(Cgmselect::Xt)
211    }
212    #[doc = "High Speed mode"]
213    #[inline(always)]
214    pub fn hs(self) -> &'a mut crate::W<REG> {
215        self.variant(Cgmselect::Hs)
216    }
217}
218impl R {
219    #[doc = "Bit 1 - Oscillator Enable"]
220    #[inline(always)]
221    pub fn enable(&self) -> EnableR {
222        EnableR::new(((self.bits >> 1) & 1) != 0)
223    }
224    #[doc = "Bit 2 - Crystal Oscillator Enable"]
225    #[inline(always)]
226    pub fn xtalen(&self) -> XtalenR {
227        XtalenR::new(((self.bits >> 2) & 1) != 0)
228    }
229    #[doc = "Bit 3 - 32kHz Output Enable"]
230    #[inline(always)]
231    pub fn en32k(&self) -> En32kR {
232        En32kR::new(((self.bits >> 3) & 1) != 0)
233    }
234    #[doc = "Bit 4 - 1kHz Output Enable"]
235    #[inline(always)]
236    pub fn en1k(&self) -> En1kR {
237        En1kR::new(((self.bits >> 4) & 1) != 0)
238    }
239    #[doc = "Bit 6 - Run in Standby"]
240    #[inline(always)]
241    pub fn runstdby(&self) -> RunstdbyR {
242        RunstdbyR::new(((self.bits >> 6) & 1) != 0)
243    }
244    #[doc = "Bit 7 - On Demand Control"]
245    #[inline(always)]
246    pub fn ondemand(&self) -> OndemandR {
247        OndemandR::new(((self.bits >> 7) & 1) != 0)
248    }
249    #[doc = "Bits 8:10 - Oscillator Start-Up Time"]
250    #[inline(always)]
251    pub fn startup(&self) -> StartupR {
252        StartupR::new(((self.bits >> 8) & 7) as u8)
253    }
254    #[doc = "Bit 12 - Write Lock"]
255    #[inline(always)]
256    pub fn wrtlock(&self) -> WrtlockR {
257        WrtlockR::new(((self.bits >> 12) & 1) != 0)
258    }
259    #[doc = "Bits 13:14 - Control Gain Mode"]
260    #[inline(always)]
261    pub fn cgm(&self) -> CgmR {
262        CgmR::new(((self.bits >> 13) & 3) as u8)
263    }
264}
265impl W {
266    #[doc = "Bit 1 - Oscillator Enable"]
267    #[inline(always)]
268    #[must_use]
269    pub fn enable(&mut self) -> EnableW<Xosc32kSpec> {
270        EnableW::new(self, 1)
271    }
272    #[doc = "Bit 2 - Crystal Oscillator Enable"]
273    #[inline(always)]
274    #[must_use]
275    pub fn xtalen(&mut self) -> XtalenW<Xosc32kSpec> {
276        XtalenW::new(self, 2)
277    }
278    #[doc = "Bit 3 - 32kHz Output Enable"]
279    #[inline(always)]
280    #[must_use]
281    pub fn en32k(&mut self) -> En32kW<Xosc32kSpec> {
282        En32kW::new(self, 3)
283    }
284    #[doc = "Bit 4 - 1kHz Output Enable"]
285    #[inline(always)]
286    #[must_use]
287    pub fn en1k(&mut self) -> En1kW<Xosc32kSpec> {
288        En1kW::new(self, 4)
289    }
290    #[doc = "Bit 6 - Run in Standby"]
291    #[inline(always)]
292    #[must_use]
293    pub fn runstdby(&mut self) -> RunstdbyW<Xosc32kSpec> {
294        RunstdbyW::new(self, 6)
295    }
296    #[doc = "Bit 7 - On Demand Control"]
297    #[inline(always)]
298    #[must_use]
299    pub fn ondemand(&mut self) -> OndemandW<Xosc32kSpec> {
300        OndemandW::new(self, 7)
301    }
302    #[doc = "Bits 8:10 - Oscillator Start-Up Time"]
303    #[inline(always)]
304    #[must_use]
305    pub fn startup(&mut self) -> StartupW<Xosc32kSpec> {
306        StartupW::new(self, 8)
307    }
308    #[doc = "Bit 12 - Write Lock"]
309    #[inline(always)]
310    #[must_use]
311    pub fn wrtlock(&mut self) -> WrtlockW<Xosc32kSpec> {
312        WrtlockW::new(self, 12)
313    }
314    #[doc = "Bits 13:14 - Control Gain Mode"]
315    #[inline(always)]
316    #[must_use]
317    pub fn cgm(&mut self) -> CgmW<Xosc32kSpec> {
318        CgmW::new(self, 13)
319    }
320}
321#[doc = "32kHz External Crystal Oscillator (XOSC32K) Control\n\nYou can [`read`](crate::Reg::read) this register and get [`xosc32k::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`xosc32k::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
322pub struct Xosc32kSpec;
323impl crate::RegisterSpec for Xosc32kSpec {
324    type Ux = u16;
325}
326#[doc = "`read()` method returns [`xosc32k::R`](R) reader structure"]
327impl crate::Readable for Xosc32kSpec {}
328#[doc = "`write(|w| ..)` method takes [`xosc32k::W`](W) writer structure"]
329impl crate::Writable for Xosc32kSpec {
330    type Safety = crate::Unsafe;
331    const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0;
332    const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0;
333}
334#[doc = "`reset()` method sets XOSC32K to value 0x2080"]
335impl crate::Resettable for Xosc32kSpec {
336    const RESET_VALUE: u16 = 0x2080;
337}
atsamd51n/osc32kctrl/xosc32k.rs

atsamd51n/osc32kctrl/
xosc32k.rs
