atsamd51n/i2s/
clkctrl.rs

1#[doc = "Register `CLKCTRL[%s]` reader"]
2pub type R = crate::R<ClkctrlSpec>;
3#[doc = "Register `CLKCTRL[%s]` writer"]
4pub type W = crate::W<ClkctrlSpec>;
5#[doc = "Slot Size\n\nValue on reset: 0"]
6#[derive(Clone, Copy, Debug, PartialEq, Eq)]
7#[repr(u8)]
8pub enum Slotsizeselect {
9    #[doc = "0: 8-bit Slot for Clock Unit n"]
10    _8 = 0,
11    #[doc = "1: 16-bit Slot for Clock Unit n"]
12    _16 = 1,
13    #[doc = "2: 24-bit Slot for Clock Unit n"]
14    _24 = 2,
15    #[doc = "3: 32-bit Slot for Clock Unit n"]
16    _32 = 3,
17}
18impl From<Slotsizeselect> for u8 {
19    #[inline(always)]
20    fn from(variant: Slotsizeselect) -> Self {
21        variant as _
22    }
23}
24impl crate::FieldSpec for Slotsizeselect {
25    type Ux = u8;
26}
27impl crate::IsEnum for Slotsizeselect {}
28#[doc = "Field `SLOTSIZE` reader - Slot Size"]
29pub type SlotsizeR = crate::FieldReader<Slotsizeselect>;
30impl SlotsizeR {
31    #[doc = "Get enumerated values variant"]
32    #[inline(always)]
33    pub const fn variant(&self) -> Slotsizeselect {
34        match self.bits {
35            0 => Slotsizeselect::_8,
36            1 => Slotsizeselect::_16,
37            2 => Slotsizeselect::_24,
38            3 => Slotsizeselect::_32,
39            _ => unreachable!(),
40        }
41    }
42    #[doc = "8-bit Slot for Clock Unit n"]
43    #[inline(always)]
44    pub fn is_8(&self) -> bool {
45        *self == Slotsizeselect::_8
46    }
47    #[doc = "16-bit Slot for Clock Unit n"]
48    #[inline(always)]
49    pub fn is_16(&self) -> bool {
50        *self == Slotsizeselect::_16
51    }
52    #[doc = "24-bit Slot for Clock Unit n"]
53    #[inline(always)]
54    pub fn is_24(&self) -> bool {
55        *self == Slotsizeselect::_24
56    }
57    #[doc = "32-bit Slot for Clock Unit n"]
58    #[inline(always)]
59    pub fn is_32(&self) -> bool {
60        *self == Slotsizeselect::_32
61    }
62}
63#[doc = "Field `SLOTSIZE` writer - Slot Size"]
64pub type SlotsizeW<'a, REG> = crate::FieldWriter<'a, REG, 2, Slotsizeselect, crate::Safe>;
65impl<'a, REG> SlotsizeW<'a, REG>
66where
67    REG: crate::Writable + crate::RegisterSpec,
68    REG::Ux: From<u8>,
69{
70    #[doc = "8-bit Slot for Clock Unit n"]
71    #[inline(always)]
72    pub fn _8(self) -> &'a mut crate::W<REG> {
73        self.variant(Slotsizeselect::_8)
74    }
75    #[doc = "16-bit Slot for Clock Unit n"]
76    #[inline(always)]
77    pub fn _16(self) -> &'a mut crate::W<REG> {
78        self.variant(Slotsizeselect::_16)
79    }
80    #[doc = "24-bit Slot for Clock Unit n"]
81    #[inline(always)]
82    pub fn _24(self) -> &'a mut crate::W<REG> {
83        self.variant(Slotsizeselect::_24)
84    }
85    #[doc = "32-bit Slot for Clock Unit n"]
86    #[inline(always)]
87    pub fn _32(self) -> &'a mut crate::W<REG> {
88        self.variant(Slotsizeselect::_32)
89    }
90}
91#[doc = "Field `NBSLOTS` reader - Number of Slots in Frame"]
92pub type NbslotsR = crate::FieldReader;
93#[doc = "Field `NBSLOTS` writer - Number of Slots in Frame"]
94pub type NbslotsW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
95#[doc = "Frame Sync Width\n\nValue on reset: 0"]
96#[derive(Clone, Copy, Debug, PartialEq, Eq)]
97#[repr(u8)]
98pub enum Fswidthselect {
99    #[doc = "0: Frame Sync Pulse is 1 Slot wide (default for I2S protocol)"]
100    Slot = 0,
101    #[doc = "1: Frame Sync Pulse is half a Frame wide"]
102    Half = 1,
103    #[doc = "2: Frame Sync Pulse is 1 Bit wide"]
104    Bit = 2,
105    #[doc = "3: Clock Unit n operates in Burst mode, with a 1-bit wide Frame Sync pulse per Data sample, only when Data transfer is requested"]
106    Burst = 3,
107}
108impl From<Fswidthselect> for u8 {
109    #[inline(always)]
110    fn from(variant: Fswidthselect) -> Self {
111        variant as _
112    }
113}
114impl crate::FieldSpec for Fswidthselect {
115    type Ux = u8;
116}
117impl crate::IsEnum for Fswidthselect {}
118#[doc = "Field `FSWIDTH` reader - Frame Sync Width"]
119pub type FswidthR = crate::FieldReader<Fswidthselect>;
120impl FswidthR {
121    #[doc = "Get enumerated values variant"]
122    #[inline(always)]
123    pub const fn variant(&self) -> Fswidthselect {
124        match self.bits {
125            0 => Fswidthselect::Slot,
126            1 => Fswidthselect::Half,
127            2 => Fswidthselect::Bit,
128            3 => Fswidthselect::Burst,
129            _ => unreachable!(),
130        }
131    }
132    #[doc = "Frame Sync Pulse is 1 Slot wide (default for I2S protocol)"]
133    #[inline(always)]
134    pub fn is_slot(&self) -> bool {
135        *self == Fswidthselect::Slot
136    }
137    #[doc = "Frame Sync Pulse is half a Frame wide"]
138    #[inline(always)]
139    pub fn is_half(&self) -> bool {
140        *self == Fswidthselect::Half
141    }
142    #[doc = "Frame Sync Pulse is 1 Bit wide"]
143    #[inline(always)]
144    pub fn is_bit(&self) -> bool {
145        *self == Fswidthselect::Bit
146    }
147    #[doc = "Clock Unit n operates in Burst mode, with a 1-bit wide Frame Sync pulse per Data sample, only when Data transfer is requested"]
148    #[inline(always)]
149    pub fn is_burst(&self) -> bool {
150        *self == Fswidthselect::Burst
151    }
152}
153#[doc = "Field `FSWIDTH` writer - Frame Sync Width"]
154pub type FswidthW<'a, REG> = crate::FieldWriter<'a, REG, 2, Fswidthselect, crate::Safe>;
155impl<'a, REG> FswidthW<'a, REG>
156where
157    REG: crate::Writable + crate::RegisterSpec,
158    REG::Ux: From<u8>,
159{
160    #[doc = "Frame Sync Pulse is 1 Slot wide (default for I2S protocol)"]
161    #[inline(always)]
162    pub fn slot(self) -> &'a mut crate::W<REG> {
163        self.variant(Fswidthselect::Slot)
164    }
165    #[doc = "Frame Sync Pulse is half a Frame wide"]
166    #[inline(always)]
167    pub fn half(self) -> &'a mut crate::W<REG> {
168        self.variant(Fswidthselect::Half)
169    }
170    #[doc = "Frame Sync Pulse is 1 Bit wide"]
171    #[inline(always)]
172    pub fn bit_(self) -> &'a mut crate::W<REG> {
173        self.variant(Fswidthselect::Bit)
174    }
175    #[doc = "Clock Unit n operates in Burst mode, with a 1-bit wide Frame Sync pulse per Data sample, only when Data transfer is requested"]
176    #[inline(always)]
177    pub fn burst(self) -> &'a mut crate::W<REG> {
178        self.variant(Fswidthselect::Burst)
179    }
180}
181#[doc = "Data Delay from Frame Sync\n\nValue on reset: 0"]
182#[derive(Clone, Copy, Debug, PartialEq, Eq)]
183pub enum Bitdelayselect {
184    #[doc = "0: Left Justified (0 Bit Delay)"]
185    Lj = 0,
186    #[doc = "1: I2S (1 Bit Delay)"]
187    I2s = 1,
188}
189impl From<Bitdelayselect> for bool {
190    #[inline(always)]
191    fn from(variant: Bitdelayselect) -> Self {
192        variant as u8 != 0
193    }
194}
195#[doc = "Field `BITDELAY` reader - Data Delay from Frame Sync"]
196pub type BitdelayR = crate::BitReader<Bitdelayselect>;
197impl BitdelayR {
198    #[doc = "Get enumerated values variant"]
199    #[inline(always)]
200    pub const fn variant(&self) -> Bitdelayselect {
201        match self.bits {
202            false => Bitdelayselect::Lj,
203            true => Bitdelayselect::I2s,
204        }
205    }
206    #[doc = "Left Justified (0 Bit Delay)"]
207    #[inline(always)]
208    pub fn is_lj(&self) -> bool {
209        *self == Bitdelayselect::Lj
210    }
211    #[doc = "I2S (1 Bit Delay)"]
212    #[inline(always)]
213    pub fn is_i2s(&self) -> bool {
214        *self == Bitdelayselect::I2s
215    }
216}
217#[doc = "Field `BITDELAY` writer - Data Delay from Frame Sync"]
218pub type BitdelayW<'a, REG> = crate::BitWriter<'a, REG, Bitdelayselect>;
219impl<'a, REG> BitdelayW<'a, REG>
220where
221    REG: crate::Writable + crate::RegisterSpec,
222{
223    #[doc = "Left Justified (0 Bit Delay)"]
224    #[inline(always)]
225    pub fn lj(self) -> &'a mut crate::W<REG> {
226        self.variant(Bitdelayselect::Lj)
227    }
228    #[doc = "I2S (1 Bit Delay)"]
229    #[inline(always)]
230    pub fn i2s(self) -> &'a mut crate::W<REG> {
231        self.variant(Bitdelayselect::I2s)
232    }
233}
234#[doc = "Frame Sync Select\n\nValue on reset: 0"]
235#[derive(Clone, Copy, Debug, PartialEq, Eq)]
236pub enum Fsselselect {
237    #[doc = "0: Divided Serial Clock n is used as Frame Sync n source"]
238    Sckdiv = 0,
239    #[doc = "1: FSn input pin is used as Frame Sync n source"]
240    Fspin = 1,
241}
242impl From<Fsselselect> for bool {
243    #[inline(always)]
244    fn from(variant: Fsselselect) -> Self {
245        variant as u8 != 0
246    }
247}
248#[doc = "Field `FSSEL` reader - Frame Sync Select"]
249pub type FsselR = crate::BitReader<Fsselselect>;
250impl FsselR {
251    #[doc = "Get enumerated values variant"]
252    #[inline(always)]
253    pub const fn variant(&self) -> Fsselselect {
254        match self.bits {
255            false => Fsselselect::Sckdiv,
256            true => Fsselselect::Fspin,
257        }
258    }
259    #[doc = "Divided Serial Clock n is used as Frame Sync n source"]
260    #[inline(always)]
261    pub fn is_sckdiv(&self) -> bool {
262        *self == Fsselselect::Sckdiv
263    }
264    #[doc = "FSn input pin is used as Frame Sync n source"]
265    #[inline(always)]
266    pub fn is_fspin(&self) -> bool {
267        *self == Fsselselect::Fspin
268    }
269}
270#[doc = "Field `FSSEL` writer - Frame Sync Select"]
271pub type FsselW<'a, REG> = crate::BitWriter<'a, REG, Fsselselect>;
272impl<'a, REG> FsselW<'a, REG>
273where
274    REG: crate::Writable + crate::RegisterSpec,
275{
276    #[doc = "Divided Serial Clock n is used as Frame Sync n source"]
277    #[inline(always)]
278    pub fn sckdiv(self) -> &'a mut crate::W<REG> {
279        self.variant(Fsselselect::Sckdiv)
280    }
281    #[doc = "FSn input pin is used as Frame Sync n source"]
282    #[inline(always)]
283    pub fn fspin(self) -> &'a mut crate::W<REG> {
284        self.variant(Fsselselect::Fspin)
285    }
286}
287#[doc = "Field `FSINV` reader - Frame Sync Invert"]
288pub type FsinvR = crate::BitReader;
289#[doc = "Field `FSINV` writer - Frame Sync Invert"]
290pub type FsinvW<'a, REG> = crate::BitWriter<'a, REG>;
291#[doc = "Field `FSOUTINV` reader - Frame Sync Output Invert"]
292pub type FsoutinvR = crate::BitReader;
293#[doc = "Field `FSOUTINV` writer - Frame Sync Output Invert"]
294pub type FsoutinvW<'a, REG> = crate::BitWriter<'a, REG>;
295#[doc = "Serial Clock Select\n\nValue on reset: 0"]
296#[derive(Clone, Copy, Debug, PartialEq, Eq)]
297pub enum Sckselselect {
298    #[doc = "0: Divided Master Clock n is used as Serial Clock n source"]
299    Mckdiv = 0,
300    #[doc = "1: SCKn input pin is used as Serial Clock n source"]
301    Sckpin = 1,
302}
303impl From<Sckselselect> for bool {
304    #[inline(always)]
305    fn from(variant: Sckselselect) -> Self {
306        variant as u8 != 0
307    }
308}
309#[doc = "Field `SCKSEL` reader - Serial Clock Select"]
310pub type SckselR = crate::BitReader<Sckselselect>;
311impl SckselR {
312    #[doc = "Get enumerated values variant"]
313    #[inline(always)]
314    pub const fn variant(&self) -> Sckselselect {
315        match self.bits {
316            false => Sckselselect::Mckdiv,
317            true => Sckselselect::Sckpin,
318        }
319    }
320    #[doc = "Divided Master Clock n is used as Serial Clock n source"]
321    #[inline(always)]
322    pub fn is_mckdiv(&self) -> bool {
323        *self == Sckselselect::Mckdiv
324    }
325    #[doc = "SCKn input pin is used as Serial Clock n source"]
326    #[inline(always)]
327    pub fn is_sckpin(&self) -> bool {
328        *self == Sckselselect::Sckpin
329    }
330}
331#[doc = "Field `SCKSEL` writer - Serial Clock Select"]
332pub type SckselW<'a, REG> = crate::BitWriter<'a, REG, Sckselselect>;
333impl<'a, REG> SckselW<'a, REG>
334where
335    REG: crate::Writable + crate::RegisterSpec,
336{
337    #[doc = "Divided Master Clock n is used as Serial Clock n source"]
338    #[inline(always)]
339    pub fn mckdiv(self) -> &'a mut crate::W<REG> {
340        self.variant(Sckselselect::Mckdiv)
341    }
342    #[doc = "SCKn input pin is used as Serial Clock n source"]
343    #[inline(always)]
344    pub fn sckpin(self) -> &'a mut crate::W<REG> {
345        self.variant(Sckselselect::Sckpin)
346    }
347}
348#[doc = "Field `SCKOUTINV` reader - Serial Clock Output Invert"]
349pub type SckoutinvR = crate::BitReader;
350#[doc = "Field `SCKOUTINV` writer - Serial Clock Output Invert"]
351pub type SckoutinvW<'a, REG> = crate::BitWriter<'a, REG>;
352#[doc = "Master Clock Select\n\nValue on reset: 0"]
353#[derive(Clone, Copy, Debug, PartialEq, Eq)]
354pub enum Mckselselect {
355    #[doc = "0: GCLK_I2S_n is used as Master Clock n source"]
356    Gclk = 0,
357    #[doc = "1: MCKn input pin is used as Master Clock n source"]
358    Mckpin = 1,
359}
360impl From<Mckselselect> for bool {
361    #[inline(always)]
362    fn from(variant: Mckselselect) -> Self {
363        variant as u8 != 0
364    }
365}
366#[doc = "Field `MCKSEL` reader - Master Clock Select"]
367pub type MckselR = crate::BitReader<Mckselselect>;
368impl MckselR {
369    #[doc = "Get enumerated values variant"]
370    #[inline(always)]
371    pub const fn variant(&self) -> Mckselselect {
372        match self.bits {
373            false => Mckselselect::Gclk,
374            true => Mckselselect::Mckpin,
375        }
376    }
377    #[doc = "GCLK_I2S_n is used as Master Clock n source"]
378    #[inline(always)]
379    pub fn is_gclk(&self) -> bool {
380        *self == Mckselselect::Gclk
381    }
382    #[doc = "MCKn input pin is used as Master Clock n source"]
383    #[inline(always)]
384    pub fn is_mckpin(&self) -> bool {
385        *self == Mckselselect::Mckpin
386    }
387}
388#[doc = "Field `MCKSEL` writer - Master Clock Select"]
389pub type MckselW<'a, REG> = crate::BitWriter<'a, REG, Mckselselect>;
390impl<'a, REG> MckselW<'a, REG>
391where
392    REG: crate::Writable + crate::RegisterSpec,
393{
394    #[doc = "GCLK_I2S_n is used as Master Clock n source"]
395    #[inline(always)]
396    pub fn gclk(self) -> &'a mut crate::W<REG> {
397        self.variant(Mckselselect::Gclk)
398    }
399    #[doc = "MCKn input pin is used as Master Clock n source"]
400    #[inline(always)]
401    pub fn mckpin(self) -> &'a mut crate::W<REG> {
402        self.variant(Mckselselect::Mckpin)
403    }
404}
405#[doc = "Field `MCKEN` reader - Master Clock Enable"]
406pub type MckenR = crate::BitReader;
407#[doc = "Field `MCKEN` writer - Master Clock Enable"]
408pub type MckenW<'a, REG> = crate::BitWriter<'a, REG>;
409#[doc = "Field `MCKOUTINV` reader - Master Clock Output Invert"]
410pub type MckoutinvR = crate::BitReader;
411#[doc = "Field `MCKOUTINV` writer - Master Clock Output Invert"]
412pub type MckoutinvW<'a, REG> = crate::BitWriter<'a, REG>;
413#[doc = "Field `MCKDIV` reader - Master Clock Division Factor"]
414pub type MckdivR = crate::FieldReader;
415#[doc = "Field `MCKDIV` writer - Master Clock Division Factor"]
416pub type MckdivW<'a, REG> = crate::FieldWriter<'a, REG, 6>;
417#[doc = "Field `MCKOUTDIV` reader - Master Clock Output Division Factor"]
418pub type MckoutdivR = crate::FieldReader;
419#[doc = "Field `MCKOUTDIV` writer - Master Clock Output Division Factor"]
420pub type MckoutdivW<'a, REG> = crate::FieldWriter<'a, REG, 6>;
421impl R {
422    #[doc = "Bits 0:1 - Slot Size"]
423    #[inline(always)]
424    pub fn slotsize(&self) -> SlotsizeR {
425        SlotsizeR::new((self.bits & 3) as u8)
426    }
427    #[doc = "Bits 2:4 - Number of Slots in Frame"]
428    #[inline(always)]
429    pub fn nbslots(&self) -> NbslotsR {
430        NbslotsR::new(((self.bits >> 2) & 7) as u8)
431    }
432    #[doc = "Bits 5:6 - Frame Sync Width"]
433    #[inline(always)]
434    pub fn fswidth(&self) -> FswidthR {
435        FswidthR::new(((self.bits >> 5) & 3) as u8)
436    }
437    #[doc = "Bit 7 - Data Delay from Frame Sync"]
438    #[inline(always)]
439    pub fn bitdelay(&self) -> BitdelayR {
440        BitdelayR::new(((self.bits >> 7) & 1) != 0)
441    }
442    #[doc = "Bit 8 - Frame Sync Select"]
443    #[inline(always)]
444    pub fn fssel(&self) -> FsselR {
445        FsselR::new(((self.bits >> 8) & 1) != 0)
446    }
447    #[doc = "Bit 9 - Frame Sync Invert"]
448    #[inline(always)]
449    pub fn fsinv(&self) -> FsinvR {
450        FsinvR::new(((self.bits >> 9) & 1) != 0)
451    }
452    #[doc = "Bit 10 - Frame Sync Output Invert"]
453    #[inline(always)]
454    pub fn fsoutinv(&self) -> FsoutinvR {
455        FsoutinvR::new(((self.bits >> 10) & 1) != 0)
456    }
457    #[doc = "Bit 11 - Serial Clock Select"]
458    #[inline(always)]
459    pub fn scksel(&self) -> SckselR {
460        SckselR::new(((self.bits >> 11) & 1) != 0)
461    }
462    #[doc = "Bit 12 - Serial Clock Output Invert"]
463    #[inline(always)]
464    pub fn sckoutinv(&self) -> SckoutinvR {
465        SckoutinvR::new(((self.bits >> 12) & 1) != 0)
466    }
467    #[doc = "Bit 13 - Master Clock Select"]
468    #[inline(always)]
469    pub fn mcksel(&self) -> MckselR {
470        MckselR::new(((self.bits >> 13) & 1) != 0)
471    }
472    #[doc = "Bit 14 - Master Clock Enable"]
473    #[inline(always)]
474    pub fn mcken(&self) -> MckenR {
475        MckenR::new(((self.bits >> 14) & 1) != 0)
476    }
477    #[doc = "Bit 15 - Master Clock Output Invert"]
478    #[inline(always)]
479    pub fn mckoutinv(&self) -> MckoutinvR {
480        MckoutinvR::new(((self.bits >> 15) & 1) != 0)
481    }
482    #[doc = "Bits 16:21 - Master Clock Division Factor"]
483    #[inline(always)]
484    pub fn mckdiv(&self) -> MckdivR {
485        MckdivR::new(((self.bits >> 16) & 0x3f) as u8)
486    }
487    #[doc = "Bits 24:29 - Master Clock Output Division Factor"]
488    #[inline(always)]
489    pub fn mckoutdiv(&self) -> MckoutdivR {
490        MckoutdivR::new(((self.bits >> 24) & 0x3f) as u8)
491    }
492}
493impl W {
494    #[doc = "Bits 0:1 - Slot Size"]
495    #[inline(always)]
496    #[must_use]
497    pub fn slotsize(&mut self) -> SlotsizeW<ClkctrlSpec> {
498        SlotsizeW::new(self, 0)
499    }
500    #[doc = "Bits 2:4 - Number of Slots in Frame"]
501    #[inline(always)]
502    #[must_use]
503    pub fn nbslots(&mut self) -> NbslotsW<ClkctrlSpec> {
504        NbslotsW::new(self, 2)
505    }
506    #[doc = "Bits 5:6 - Frame Sync Width"]
507    #[inline(always)]
508    #[must_use]
509    pub fn fswidth(&mut self) -> FswidthW<ClkctrlSpec> {
510        FswidthW::new(self, 5)
511    }
512    #[doc = "Bit 7 - Data Delay from Frame Sync"]
513    #[inline(always)]
514    #[must_use]
515    pub fn bitdelay(&mut self) -> BitdelayW<ClkctrlSpec> {
516        BitdelayW::new(self, 7)
517    }
518    #[doc = "Bit 8 - Frame Sync Select"]
519    #[inline(always)]
520    #[must_use]
521    pub fn fssel(&mut self) -> FsselW<ClkctrlSpec> {
522        FsselW::new(self, 8)
523    }
524    #[doc = "Bit 9 - Frame Sync Invert"]
525    #[inline(always)]
526    #[must_use]
527    pub fn fsinv(&mut self) -> FsinvW<ClkctrlSpec> {
528        FsinvW::new(self, 9)
529    }
530    #[doc = "Bit 10 - Frame Sync Output Invert"]
531    #[inline(always)]
532    #[must_use]
533    pub fn fsoutinv(&mut self) -> FsoutinvW<ClkctrlSpec> {
534        FsoutinvW::new(self, 10)
535    }
536    #[doc = "Bit 11 - Serial Clock Select"]
537    #[inline(always)]
538    #[must_use]
539    pub fn scksel(&mut self) -> SckselW<ClkctrlSpec> {
540        SckselW::new(self, 11)
541    }
542    #[doc = "Bit 12 - Serial Clock Output Invert"]
543    #[inline(always)]
544    #[must_use]
545    pub fn sckoutinv(&mut self) -> SckoutinvW<ClkctrlSpec> {
546        SckoutinvW::new(self, 12)
547    }
548    #[doc = "Bit 13 - Master Clock Select"]
549    #[inline(always)]
550    #[must_use]
551    pub fn mcksel(&mut self) -> MckselW<ClkctrlSpec> {
552        MckselW::new(self, 13)
553    }
554    #[doc = "Bit 14 - Master Clock Enable"]
555    #[inline(always)]
556    #[must_use]
557    pub fn mcken(&mut self) -> MckenW<ClkctrlSpec> {
558        MckenW::new(self, 14)
559    }
560    #[doc = "Bit 15 - Master Clock Output Invert"]
561    #[inline(always)]
562    #[must_use]
563    pub fn mckoutinv(&mut self) -> MckoutinvW<ClkctrlSpec> {
564        MckoutinvW::new(self, 15)
565    }
566    #[doc = "Bits 16:21 - Master Clock Division Factor"]
567    #[inline(always)]
568    #[must_use]
569    pub fn mckdiv(&mut self) -> MckdivW<ClkctrlSpec> {
570        MckdivW::new(self, 16)
571    }
572    #[doc = "Bits 24:29 - Master Clock Output Division Factor"]
573    #[inline(always)]
574    #[must_use]
575    pub fn mckoutdiv(&mut self) -> MckoutdivW<ClkctrlSpec> {
576        MckoutdivW::new(self, 24)
577    }
578}
579#[doc = "Clock Unit n Control\n\nYou can [`read`](crate::Reg::read) this register and get [`clkctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clkctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
580pub struct ClkctrlSpec;
581impl crate::RegisterSpec for ClkctrlSpec {
582    type Ux = u32;
583}
584#[doc = "`read()` method returns [`clkctrl::R`](R) reader structure"]
585impl crate::Readable for ClkctrlSpec {}
586#[doc = "`write(|w| ..)` method takes [`clkctrl::W`](W) writer structure"]
587impl crate::Writable for ClkctrlSpec {
588    type Safety = crate::Unsafe;
589    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
590    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
591}
592#[doc = "`reset()` method sets CLKCTRL[%s]
593to value 0"]
594impl crate::Resettable for ClkctrlSpec {
595    const RESET_VALUE: u32 = 0;
596}
atsamd51n/i2s/clkctrl.rs

atsamd51n/i2s/
clkctrl.rs
