atsamd51n/sercom0/i2cs/
status.rs

1#[doc = "Register `STATUS` reader"]
2pub type R = crate::R<StatusSpec>;
3#[doc = "Register `STATUS` writer"]
4pub type W = crate::W<StatusSpec>;
5#[doc = "Field `BUSERR` reader - Bus Error"]
6pub type BuserrR = crate::BitReader;
7#[doc = "Field `BUSERR` writer - Bus Error"]
8pub type BuserrW<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `COLL` reader - Transmit Collision"]
10pub type CollR = crate::BitReader;
11#[doc = "Field `COLL` writer - Transmit Collision"]
12pub type CollW<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `RXNACK` reader - Received Not Acknowledge"]
14pub type RxnackR = crate::BitReader;
15#[doc = "Field `RXNACK` writer - Received Not Acknowledge"]
16pub type RxnackW<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `DIR` reader - Read/Write Direction"]
18pub type DirR = crate::BitReader;
19#[doc = "Field `DIR` writer - Read/Write Direction"]
20pub type DirW<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `SR` reader - Repeated Start"]
22pub type SrR = crate::BitReader;
23#[doc = "Field `SR` writer - Repeated Start"]
24pub type SrW<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `LOWTOUT` reader - SCL Low Timeout"]
26pub type LowtoutR = crate::BitReader;
27#[doc = "Field `LOWTOUT` writer - SCL Low Timeout"]
28pub type LowtoutW<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `CLKHOLD` reader - Clock Hold"]
30pub type ClkholdR = crate::BitReader;
31#[doc = "Field `CLKHOLD` writer - Clock Hold"]
32pub type ClkholdW<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `SEXTTOUT` reader - Slave SCL Low Extend Timeout"]
34pub type SexttoutR = crate::BitReader;
35#[doc = "Field `SEXTTOUT` writer - Slave SCL Low Extend Timeout"]
36pub type SexttoutW<'a, REG> = crate::BitWriter<'a, REG>;
37#[doc = "Field `HS` reader - High Speed"]
38pub type HsR = crate::BitReader;
39#[doc = "Field `HS` writer - High Speed"]
40pub type HsW<'a, REG> = crate::BitWriter<'a, REG>;
41#[doc = "Field `LENERR` reader - Transaction Length Error"]
42pub type LenerrR = crate::BitReader;
43#[doc = "Field `LENERR` writer - Transaction Length Error"]
44pub type LenerrW<'a, REG> = crate::BitWriter<'a, REG>;
45impl R {
46    #[doc = "Bit 0 - Bus Error"]
47    #[inline(always)]
48    pub fn buserr(&self) -> BuserrR {
49        BuserrR::new((self.bits & 1) != 0)
50    }
51    #[doc = "Bit 1 - Transmit Collision"]
52    #[inline(always)]
53    pub fn coll(&self) -> CollR {
54        CollR::new(((self.bits >> 1) & 1) != 0)
55    }
56    #[doc = "Bit 2 - Received Not Acknowledge"]
57    #[inline(always)]
58    pub fn rxnack(&self) -> RxnackR {
59        RxnackR::new(((self.bits >> 2) & 1) != 0)
60    }
61    #[doc = "Bit 3 - Read/Write Direction"]
62    #[inline(always)]
63    pub fn dir(&self) -> DirR {
64        DirR::new(((self.bits >> 3) & 1) != 0)
65    }
66    #[doc = "Bit 4 - Repeated Start"]
67    #[inline(always)]
68    pub fn sr(&self) -> SrR {
69        SrR::new(((self.bits >> 4) & 1) != 0)
70    }
71    #[doc = "Bit 6 - SCL Low Timeout"]
72    #[inline(always)]
73    pub fn lowtout(&self) -> LowtoutR {
74        LowtoutR::new(((self.bits >> 6) & 1) != 0)
75    }
76    #[doc = "Bit 7 - Clock Hold"]
77    #[inline(always)]
78    pub fn clkhold(&self) -> ClkholdR {
79        ClkholdR::new(((self.bits >> 7) & 1) != 0)
80    }
81    #[doc = "Bit 9 - Slave SCL Low Extend Timeout"]
82    #[inline(always)]
83    pub fn sexttout(&self) -> SexttoutR {
84        SexttoutR::new(((self.bits >> 9) & 1) != 0)
85    }
86    #[doc = "Bit 10 - High Speed"]
87    #[inline(always)]
88    pub fn hs(&self) -> HsR {
89        HsR::new(((self.bits >> 10) & 1) != 0)
90    }
91    #[doc = "Bit 11 - Transaction Length Error"]
92    #[inline(always)]
93    pub fn lenerr(&self) -> LenerrR {
94        LenerrR::new(((self.bits >> 11) & 1) != 0)
95    }
96}
97impl W {
98    #[doc = "Bit 0 - Bus Error"]
99    #[inline(always)]
100    #[must_use]
101    pub fn buserr(&mut self) -> BuserrW<StatusSpec> {
102        BuserrW::new(self, 0)
103    }
104    #[doc = "Bit 1 - Transmit Collision"]
105    #[inline(always)]
106    #[must_use]
107    pub fn coll(&mut self) -> CollW<StatusSpec> {
108        CollW::new(self, 1)
109    }
110    #[doc = "Bit 2 - Received Not Acknowledge"]
111    #[inline(always)]
112    #[must_use]
113    pub fn rxnack(&mut self) -> RxnackW<StatusSpec> {
114        RxnackW::new(self, 2)
115    }
116    #[doc = "Bit 3 - Read/Write Direction"]
117    #[inline(always)]
118    #[must_use]
119    pub fn dir(&mut self) -> DirW<StatusSpec> {
120        DirW::new(self, 3)
121    }
122    #[doc = "Bit 4 - Repeated Start"]
123    #[inline(always)]
124    #[must_use]
125    pub fn sr(&mut self) -> SrW<StatusSpec> {
126        SrW::new(self, 4)
127    }
128    #[doc = "Bit 6 - SCL Low Timeout"]
129    #[inline(always)]
130    #[must_use]
131    pub fn lowtout(&mut self) -> LowtoutW<StatusSpec> {
132        LowtoutW::new(self, 6)
133    }
134    #[doc = "Bit 7 - Clock Hold"]
135    #[inline(always)]
136    #[must_use]
137    pub fn clkhold(&mut self) -> ClkholdW<StatusSpec> {
138        ClkholdW::new(self, 7)
139    }
140    #[doc = "Bit 9 - Slave SCL Low Extend Timeout"]
141    #[inline(always)]
142    #[must_use]
143    pub fn sexttout(&mut self) -> SexttoutW<StatusSpec> {
144        SexttoutW::new(self, 9)
145    }
146    #[doc = "Bit 10 - High Speed"]
147    #[inline(always)]
148    #[must_use]
149    pub fn hs(&mut self) -> HsW<StatusSpec> {
150        HsW::new(self, 10)
151    }
152    #[doc = "Bit 11 - Transaction Length Error"]
153    #[inline(always)]
154    #[must_use]
155    pub fn lenerr(&mut self) -> LenerrW<StatusSpec> {
156        LenerrW::new(self, 11)
157    }
158}
159#[doc = "I2CS Status\n\nYou can [`read`](crate::Reg::read) this register and get [`status::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`status::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
160pub struct StatusSpec;
161impl crate::RegisterSpec for StatusSpec {
162    type Ux = u16;
163}
164#[doc = "`read()` method returns [`status::R`](R) reader structure"]
165impl crate::Readable for StatusSpec {}
166#[doc = "`write(|w| ..)` method takes [`status::W`](W) writer structure"]
167impl crate::Writable for StatusSpec {
168    type Safety = crate::Unsafe;
169    const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0;
170    const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0;
171}
172#[doc = "`reset()` method sets STATUS to value 0"]
173impl crate::Resettable for StatusSpec {
174    const RESET_VALUE: u16 = 0;
175}
atsamd51n/sercom0/i2cs/status.rs

atsamd51n/sercom0/i2cs/
status.rs
