atsamd51n/sdhc0/
pvr.rs

1#[doc = "Register `PVR[%s]` reader"]
2pub type R = crate::R<PvrSpec>;
3#[doc = "Register `PVR[%s]` writer"]
4pub type W = crate::W<PvrSpec>;
5#[doc = "Field `SDCLKFSEL` reader - SDCLK Frequency Select Value for Initialization"]
6pub type SdclkfselR = crate::FieldReader<u16>;
7#[doc = "Field `SDCLKFSEL` writer - SDCLK Frequency Select Value for Initialization"]
8pub type SdclkfselW<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>;
9#[doc = "Clock Generator Select Value for Initialization\n\nValue on reset: 0"]
10#[derive(Clone, Copy, Debug, PartialEq, Eq)]
11pub enum Clkgselselect {
12    #[doc = "0: Host Controller Ver2.00 Compatible Clock Generator (Divider)"]
13    Div = 0,
14    #[doc = "1: Programmable Clock Generator"]
15    Prog = 1,
16}
17impl From<Clkgselselect> for bool {
18    #[inline(always)]
19    fn from(variant: Clkgselselect) -> Self {
20        variant as u8 != 0
21    }
22}
23#[doc = "Field `CLKGSEL` reader - Clock Generator Select Value for Initialization"]
24pub type ClkgselR = crate::BitReader<Clkgselselect>;
25impl ClkgselR {
26    #[doc = "Get enumerated values variant"]
27    #[inline(always)]
28    pub const fn variant(&self) -> Clkgselselect {
29        match self.bits {
30            false => Clkgselselect::Div,
31            true => Clkgselselect::Prog,
32        }
33    }
34    #[doc = "Host Controller Ver2.00 Compatible Clock Generator (Divider)"]
35    #[inline(always)]
36    pub fn is_div(&self) -> bool {
37        *self == Clkgselselect::Div
38    }
39    #[doc = "Programmable Clock Generator"]
40    #[inline(always)]
41    pub fn is_prog(&self) -> bool {
42        *self == Clkgselselect::Prog
43    }
44}
45#[doc = "Field `CLKGSEL` writer - Clock Generator Select Value for Initialization"]
46pub type ClkgselW<'a, REG> = crate::BitWriter<'a, REG, Clkgselselect>;
47impl<'a, REG> ClkgselW<'a, REG>
48where
49    REG: crate::Writable + crate::RegisterSpec,
50{
51    #[doc = "Host Controller Ver2.00 Compatible Clock Generator (Divider)"]
52    #[inline(always)]
53    pub fn div(self) -> &'a mut crate::W<REG> {
54        self.variant(Clkgselselect::Div)
55    }
56    #[doc = "Programmable Clock Generator"]
57    #[inline(always)]
58    pub fn prog(self) -> &'a mut crate::W<REG> {
59        self.variant(Clkgselselect::Prog)
60    }
61}
62#[doc = "Driver Strength Select Value for Initialization\n\nValue on reset: 0"]
63#[derive(Clone, Copy, Debug, PartialEq, Eq)]
64#[repr(u8)]
65pub enum Drvselselect {
66    #[doc = "0: Driver Type B is Selected"]
67    B = 0,
68    #[doc = "1: Driver Type A is Selected"]
69    A = 1,
70    #[doc = "2: Driver Type C is Selected"]
71    C = 2,
72    #[doc = "3: Driver Type D is Selected"]
73    D = 3,
74}
75impl From<Drvselselect> for u8 {
76    #[inline(always)]
77    fn from(variant: Drvselselect) -> Self {
78        variant as _
79    }
80}
81impl crate::FieldSpec for Drvselselect {
82    type Ux = u8;
83}
84impl crate::IsEnum for Drvselselect {}
85#[doc = "Field `DRVSEL` reader - Driver Strength Select Value for Initialization"]
86pub type DrvselR = crate::FieldReader<Drvselselect>;
87impl DrvselR {
88    #[doc = "Get enumerated values variant"]
89    #[inline(always)]
90    pub const fn variant(&self) -> Drvselselect {
91        match self.bits {
92            0 => Drvselselect::B,
93            1 => Drvselselect::A,
94            2 => Drvselselect::C,
95            3 => Drvselselect::D,
96            _ => unreachable!(),
97        }
98    }
99    #[doc = "Driver Type B is Selected"]
100    #[inline(always)]
101    pub fn is_b(&self) -> bool {
102        *self == Drvselselect::B
103    }
104    #[doc = "Driver Type A is Selected"]
105    #[inline(always)]
106    pub fn is_a(&self) -> bool {
107        *self == Drvselselect::A
108    }
109    #[doc = "Driver Type C is Selected"]
110    #[inline(always)]
111    pub fn is_c(&self) -> bool {
112        *self == Drvselselect::C
113    }
114    #[doc = "Driver Type D is Selected"]
115    #[inline(always)]
116    pub fn is_d(&self) -> bool {
117        *self == Drvselselect::D
118    }
119}
120#[doc = "Field `DRVSEL` writer - Driver Strength Select Value for Initialization"]
121pub type DrvselW<'a, REG> = crate::FieldWriter<'a, REG, 2, Drvselselect, crate::Safe>;
122impl<'a, REG> DrvselW<'a, REG>
123where
124    REG: crate::Writable + crate::RegisterSpec,
125    REG::Ux: From<u8>,
126{
127    #[doc = "Driver Type B is Selected"]
128    #[inline(always)]
129    pub fn b(self) -> &'a mut crate::W<REG> {
130        self.variant(Drvselselect::B)
131    }
132    #[doc = "Driver Type A is Selected"]
133    #[inline(always)]
134    pub fn a(self) -> &'a mut crate::W<REG> {
135        self.variant(Drvselselect::A)
136    }
137    #[doc = "Driver Type C is Selected"]
138    #[inline(always)]
139    pub fn c(self) -> &'a mut crate::W<REG> {
140        self.variant(Drvselselect::C)
141    }
142    #[doc = "Driver Type D is Selected"]
143    #[inline(always)]
144    pub fn d(self) -> &'a mut crate::W<REG> {
145        self.variant(Drvselselect::D)
146    }
147}
148impl R {
149    #[doc = "Bits 0:9 - SDCLK Frequency Select Value for Initialization"]
150    #[inline(always)]
151    pub fn sdclkfsel(&self) -> SdclkfselR {
152        SdclkfselR::new(self.bits & 0x03ff)
153    }
154    #[doc = "Bit 10 - Clock Generator Select Value for Initialization"]
155    #[inline(always)]
156    pub fn clkgsel(&self) -> ClkgselR {
157        ClkgselR::new(((self.bits >> 10) & 1) != 0)
158    }
159    #[doc = "Bits 14:15 - Driver Strength Select Value for Initialization"]
160    #[inline(always)]
161    pub fn drvsel(&self) -> DrvselR {
162        DrvselR::new(((self.bits >> 14) & 3) as u8)
163    }
164}
165impl W {
166    #[doc = "Bits 0:9 - SDCLK Frequency Select Value for Initialization"]
167    #[inline(always)]
168    #[must_use]
169    pub fn sdclkfsel(&mut self) -> SdclkfselW<PvrSpec> {
170        SdclkfselW::new(self, 0)
171    }
172    #[doc = "Bit 10 - Clock Generator Select Value for Initialization"]
173    #[inline(always)]
174    #[must_use]
175    pub fn clkgsel(&mut self) -> ClkgselW<PvrSpec> {
176        ClkgselW::new(self, 10)
177    }
178    #[doc = "Bits 14:15 - Driver Strength Select Value for Initialization"]
179    #[inline(always)]
180    #[must_use]
181    pub fn drvsel(&mut self) -> DrvselW<PvrSpec> {
182        DrvselW::new(self, 14)
183    }
184}
185#[doc = "Preset Value n\n\nYou can [`read`](crate::Reg::read) this register and get [`pvr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pvr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
186pub struct PvrSpec;
187impl crate::RegisterSpec for PvrSpec {
188    type Ux = u16;
189}
190#[doc = "`read()` method returns [`pvr::R`](R) reader structure"]
191impl crate::Readable for PvrSpec {}
192#[doc = "`write(|w| ..)` method takes [`pvr::W`](W) writer structure"]
193impl crate::Writable for PvrSpec {
194    type Safety = crate::Unsafe;
195    const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0;
196    const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0;
197}
198#[doc = "`reset()` method sets PVR[%s]
199to value 0"]
200impl crate::Resettable for PvrSpec {
201    const RESET_VALUE: u16 = 0;
202}
atsamd51n/sdhc0/pvr.rs

atsamd51n/sdhc0/
pvr.rs
