atsamd51n/gclk/
genctrl.rs

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1#[doc = "Register `GENCTRL[%s]` reader"]
2pub type R = crate::R<GenctrlSpec>;
3#[doc = "Register `GENCTRL[%s]` writer"]
4pub type W = crate::W<GenctrlSpec>;
5#[doc = "Source Select\n\nValue on reset: 0"]
6#[derive(Clone, Copy, Debug, PartialEq, Eq)]
7#[repr(u8)]
8pub enum Srcselect {
9    #[doc = "0: XOSC0 oscillator output"]
10    Xosc0 = 0,
11    #[doc = "1: XOSC1 oscillator output"]
12    Xosc1 = 1,
13    #[doc = "2: Generator input pad"]
14    Gclkin = 2,
15    #[doc = "3: Generic clock generator 1 output"]
16    Gclkgen1 = 3,
17    #[doc = "4: OSCULP32K oscillator output"]
18    Osculp32k = 4,
19    #[doc = "5: XOSC32K oscillator output"]
20    Xosc32k = 5,
21    #[doc = "6: DFLL output"]
22    Dfll = 6,
23    #[doc = "7: DPLL0 output"]
24    Dpll0 = 7,
25    #[doc = "8: DPLL1 output"]
26    Dpll1 = 8,
27}
28impl From<Srcselect> for u8 {
29    #[inline(always)]
30    fn from(variant: Srcselect) -> Self {
31        variant as _
32    }
33}
34impl crate::FieldSpec for Srcselect {
35    type Ux = u8;
36}
37impl crate::IsEnum for Srcselect {}
38#[doc = "Field `SRC` reader - Source Select"]
39pub type SrcR = crate::FieldReader<Srcselect>;
40impl SrcR {
41    #[doc = "Get enumerated values variant"]
42    #[inline(always)]
43    pub const fn variant(&self) -> Option<Srcselect> {
44        match self.bits {
45            0 => Some(Srcselect::Xosc0),
46            1 => Some(Srcselect::Xosc1),
47            2 => Some(Srcselect::Gclkin),
48            3 => Some(Srcselect::Gclkgen1),
49            4 => Some(Srcselect::Osculp32k),
50            5 => Some(Srcselect::Xosc32k),
51            6 => Some(Srcselect::Dfll),
52            7 => Some(Srcselect::Dpll0),
53            8 => Some(Srcselect::Dpll1),
54            _ => None,
55        }
56    }
57    #[doc = "XOSC0 oscillator output"]
58    #[inline(always)]
59    pub fn is_xosc0(&self) -> bool {
60        *self == Srcselect::Xosc0
61    }
62    #[doc = "XOSC1 oscillator output"]
63    #[inline(always)]
64    pub fn is_xosc1(&self) -> bool {
65        *self == Srcselect::Xosc1
66    }
67    #[doc = "Generator input pad"]
68    #[inline(always)]
69    pub fn is_gclkin(&self) -> bool {
70        *self == Srcselect::Gclkin
71    }
72    #[doc = "Generic clock generator 1 output"]
73    #[inline(always)]
74    pub fn is_gclkgen1(&self) -> bool {
75        *self == Srcselect::Gclkgen1
76    }
77    #[doc = "OSCULP32K oscillator output"]
78    #[inline(always)]
79    pub fn is_osculp32k(&self) -> bool {
80        *self == Srcselect::Osculp32k
81    }
82    #[doc = "XOSC32K oscillator output"]
83    #[inline(always)]
84    pub fn is_xosc32k(&self) -> bool {
85        *self == Srcselect::Xosc32k
86    }
87    #[doc = "DFLL output"]
88    #[inline(always)]
89    pub fn is_dfll(&self) -> bool {
90        *self == Srcselect::Dfll
91    }
92    #[doc = "DPLL0 output"]
93    #[inline(always)]
94    pub fn is_dpll0(&self) -> bool {
95        *self == Srcselect::Dpll0
96    }
97    #[doc = "DPLL1 output"]
98    #[inline(always)]
99    pub fn is_dpll1(&self) -> bool {
100        *self == Srcselect::Dpll1
101    }
102}
103#[doc = "Field `SRC` writer - Source Select"]
104pub type SrcW<'a, REG> = crate::FieldWriter<'a, REG, 4, Srcselect>;
105impl<'a, REG> SrcW<'a, REG>
106where
107    REG: crate::Writable + crate::RegisterSpec,
108    REG::Ux: From<u8>,
109{
110    #[doc = "XOSC0 oscillator output"]
111    #[inline(always)]
112    pub fn xosc0(self) -> &'a mut crate::W<REG> {
113        self.variant(Srcselect::Xosc0)
114    }
115    #[doc = "XOSC1 oscillator output"]
116    #[inline(always)]
117    pub fn xosc1(self) -> &'a mut crate::W<REG> {
118        self.variant(Srcselect::Xosc1)
119    }
120    #[doc = "Generator input pad"]
121    #[inline(always)]
122    pub fn gclkin(self) -> &'a mut crate::W<REG> {
123        self.variant(Srcselect::Gclkin)
124    }
125    #[doc = "Generic clock generator 1 output"]
126    #[inline(always)]
127    pub fn gclkgen1(self) -> &'a mut crate::W<REG> {
128        self.variant(Srcselect::Gclkgen1)
129    }
130    #[doc = "OSCULP32K oscillator output"]
131    #[inline(always)]
132    pub fn osculp32k(self) -> &'a mut crate::W<REG> {
133        self.variant(Srcselect::Osculp32k)
134    }
135    #[doc = "XOSC32K oscillator output"]
136    #[inline(always)]
137    pub fn xosc32k(self) -> &'a mut crate::W<REG> {
138        self.variant(Srcselect::Xosc32k)
139    }
140    #[doc = "DFLL output"]
141    #[inline(always)]
142    pub fn dfll(self) -> &'a mut crate::W<REG> {
143        self.variant(Srcselect::Dfll)
144    }
145    #[doc = "DPLL0 output"]
146    #[inline(always)]
147    pub fn dpll0(self) -> &'a mut crate::W<REG> {
148        self.variant(Srcselect::Dpll0)
149    }
150    #[doc = "DPLL1 output"]
151    #[inline(always)]
152    pub fn dpll1(self) -> &'a mut crate::W<REG> {
153        self.variant(Srcselect::Dpll1)
154    }
155}
156#[doc = "Field `GENEN` reader - Generic Clock Generator Enable"]
157pub type GenenR = crate::BitReader;
158#[doc = "Field `GENEN` writer - Generic Clock Generator Enable"]
159pub type GenenW<'a, REG> = crate::BitWriter<'a, REG>;
160#[doc = "Field `IDC` reader - Improve Duty Cycle"]
161pub type IdcR = crate::BitReader;
162#[doc = "Field `IDC` writer - Improve Duty Cycle"]
163pub type IdcW<'a, REG> = crate::BitWriter<'a, REG>;
164#[doc = "Field `OOV` reader - Output Off Value"]
165pub type OovR = crate::BitReader;
166#[doc = "Field `OOV` writer - Output Off Value"]
167pub type OovW<'a, REG> = crate::BitWriter<'a, REG>;
168#[doc = "Field `OE` reader - Output Enable"]
169pub type OeR = crate::BitReader;
170#[doc = "Field `OE` writer - Output Enable"]
171pub type OeW<'a, REG> = crate::BitWriter<'a, REG>;
172#[doc = "Divide Selection\n\nValue on reset: 0"]
173#[derive(Clone, Copy, Debug, PartialEq, Eq)]
174pub enum Divselselect {
175    #[doc = "0: Divide input directly by divider factor"]
176    Div1 = 0,
177    #[doc = "1: Divide input by 2^(divider factor+ 1)"]
178    Div2 = 1,
179}
180impl From<Divselselect> for bool {
181    #[inline(always)]
182    fn from(variant: Divselselect) -> Self {
183        variant as u8 != 0
184    }
185}
186#[doc = "Field `DIVSEL` reader - Divide Selection"]
187pub type DivselR = crate::BitReader<Divselselect>;
188impl DivselR {
189    #[doc = "Get enumerated values variant"]
190    #[inline(always)]
191    pub const fn variant(&self) -> Divselselect {
192        match self.bits {
193            false => Divselselect::Div1,
194            true => Divselselect::Div2,
195        }
196    }
197    #[doc = "Divide input directly by divider factor"]
198    #[inline(always)]
199    pub fn is_div1(&self) -> bool {
200        *self == Divselselect::Div1
201    }
202    #[doc = "Divide input by 2^(divider factor+ 1)"]
203    #[inline(always)]
204    pub fn is_div2(&self) -> bool {
205        *self == Divselselect::Div2
206    }
207}
208#[doc = "Field `DIVSEL` writer - Divide Selection"]
209pub type DivselW<'a, REG> = crate::BitWriter<'a, REG, Divselselect>;
210impl<'a, REG> DivselW<'a, REG>
211where
212    REG: crate::Writable + crate::RegisterSpec,
213{
214    #[doc = "Divide input directly by divider factor"]
215    #[inline(always)]
216    pub fn div1(self) -> &'a mut crate::W<REG> {
217        self.variant(Divselselect::Div1)
218    }
219    #[doc = "Divide input by 2^(divider factor+ 1)"]
220    #[inline(always)]
221    pub fn div2(self) -> &'a mut crate::W<REG> {
222        self.variant(Divselselect::Div2)
223    }
224}
225#[doc = "Field `RUNSTDBY` reader - Run in Standby"]
226pub type RunstdbyR = crate::BitReader;
227#[doc = "Field `RUNSTDBY` writer - Run in Standby"]
228pub type RunstdbyW<'a, REG> = crate::BitWriter<'a, REG>;
229#[doc = "Field `DIV` reader - Division Factor"]
230pub type DivR = crate::FieldReader<u16>;
231#[doc = "Field `DIV` writer - Division Factor"]
232pub type DivW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
233impl R {
234    #[doc = "Bits 0:3 - Source Select"]
235    #[inline(always)]
236    pub fn src(&self) -> SrcR {
237        SrcR::new((self.bits & 0x0f) as u8)
238    }
239    #[doc = "Bit 8 - Generic Clock Generator Enable"]
240    #[inline(always)]
241    pub fn genen(&self) -> GenenR {
242        GenenR::new(((self.bits >> 8) & 1) != 0)
243    }
244    #[doc = "Bit 9 - Improve Duty Cycle"]
245    #[inline(always)]
246    pub fn idc(&self) -> IdcR {
247        IdcR::new(((self.bits >> 9) & 1) != 0)
248    }
249    #[doc = "Bit 10 - Output Off Value"]
250    #[inline(always)]
251    pub fn oov(&self) -> OovR {
252        OovR::new(((self.bits >> 10) & 1) != 0)
253    }
254    #[doc = "Bit 11 - Output Enable"]
255    #[inline(always)]
256    pub fn oe(&self) -> OeR {
257        OeR::new(((self.bits >> 11) & 1) != 0)
258    }
259    #[doc = "Bit 12 - Divide Selection"]
260    #[inline(always)]
261    pub fn divsel(&self) -> DivselR {
262        DivselR::new(((self.bits >> 12) & 1) != 0)
263    }
264    #[doc = "Bit 13 - Run in Standby"]
265    #[inline(always)]
266    pub fn runstdby(&self) -> RunstdbyR {
267        RunstdbyR::new(((self.bits >> 13) & 1) != 0)
268    }
269    #[doc = "Bits 16:31 - Division Factor"]
270    #[inline(always)]
271    pub fn div(&self) -> DivR {
272        DivR::new(((self.bits >> 16) & 0xffff) as u16)
273    }
274}
275impl W {
276    #[doc = "Bits 0:3 - Source Select"]
277    #[inline(always)]
278    #[must_use]
279    pub fn src(&mut self) -> SrcW<GenctrlSpec> {
280        SrcW::new(self, 0)
281    }
282    #[doc = "Bit 8 - Generic Clock Generator Enable"]
283    #[inline(always)]
284    #[must_use]
285    pub fn genen(&mut self) -> GenenW<GenctrlSpec> {
286        GenenW::new(self, 8)
287    }
288    #[doc = "Bit 9 - Improve Duty Cycle"]
289    #[inline(always)]
290    #[must_use]
291    pub fn idc(&mut self) -> IdcW<GenctrlSpec> {
292        IdcW::new(self, 9)
293    }
294    #[doc = "Bit 10 - Output Off Value"]
295    #[inline(always)]
296    #[must_use]
297    pub fn oov(&mut self) -> OovW<GenctrlSpec> {
298        OovW::new(self, 10)
299    }
300    #[doc = "Bit 11 - Output Enable"]
301    #[inline(always)]
302    #[must_use]
303    pub fn oe(&mut self) -> OeW<GenctrlSpec> {
304        OeW::new(self, 11)
305    }
306    #[doc = "Bit 12 - Divide Selection"]
307    #[inline(always)]
308    #[must_use]
309    pub fn divsel(&mut self) -> DivselW<GenctrlSpec> {
310        DivselW::new(self, 12)
311    }
312    #[doc = "Bit 13 - Run in Standby"]
313    #[inline(always)]
314    #[must_use]
315    pub fn runstdby(&mut self) -> RunstdbyW<GenctrlSpec> {
316        RunstdbyW::new(self, 13)
317    }
318    #[doc = "Bits 16:31 - Division Factor"]
319    #[inline(always)]
320    #[must_use]
321    pub fn div(&mut self) -> DivW<GenctrlSpec> {
322        DivW::new(self, 16)
323    }
324}
325#[doc = "Generic Clock Generator Control\n\nYou can [`read`](crate::Reg::read) this register and get [`genctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`genctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
326pub struct GenctrlSpec;
327impl crate::RegisterSpec for GenctrlSpec {
328    type Ux = u32;
329}
330#[doc = "`read()` method returns [`genctrl::R`](R) reader structure"]
331impl crate::Readable for GenctrlSpec {}
332#[doc = "`write(|w| ..)` method takes [`genctrl::W`](W) writer structure"]
333impl crate::Writable for GenctrlSpec {
334    type Safety = crate::Unsafe;
335    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
336    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
337}
338#[doc = "`reset()` method sets GENCTRL[%s]
339to value 0"]
340impl crate::Resettable for GenctrlSpec {
341    const RESET_VALUE: u32 = 0;
342}
atsamd51n/gclk/genctrl.rs

atsamd51n/gclk/
genctrl.rs
