atsamd51n/mclk/
cpudiv.rs

1#[doc = "Register `CPUDIV` reader"]
2pub type R = crate::R<CpudivSpec>;
3#[doc = "Register `CPUDIV` writer"]
4pub type W = crate::W<CpudivSpec>;
5#[doc = "Low-Power Clock Division Factor\n\nValue on reset: 1"]
6#[derive(Clone, Copy, Debug, PartialEq, Eq)]
7#[repr(u8)]
8pub enum Divselect {
9    #[doc = "1: Divide by 1"]
10    Div1 = 1,
11    #[doc = "2: Divide by 2"]
12    Div2 = 2,
13    #[doc = "4: Divide by 4"]
14    Div4 = 4,
15    #[doc = "8: Divide by 8"]
16    Div8 = 8,
17    #[doc = "16: Divide by 16"]
18    Div16 = 16,
19    #[doc = "32: Divide by 32"]
20    Div32 = 32,
21    #[doc = "64: Divide by 64"]
22    Div64 = 64,
23    #[doc = "128: Divide by 128"]
24    Div128 = 128,
25}
26impl From<Divselect> for u8 {
27    #[inline(always)]
28    fn from(variant: Divselect) -> Self {
29        variant as _
30    }
31}
32impl crate::FieldSpec for Divselect {
33    type Ux = u8;
34}
35impl crate::IsEnum for Divselect {}
36#[doc = "Field `DIV` reader - Low-Power Clock Division Factor"]
37pub type DivR = crate::FieldReader<Divselect>;
38impl DivR {
39    #[doc = "Get enumerated values variant"]
40    #[inline(always)]
41    pub const fn variant(&self) -> Option<Divselect> {
42        match self.bits {
43            1 => Some(Divselect::Div1),
44            2 => Some(Divselect::Div2),
45            4 => Some(Divselect::Div4),
46            8 => Some(Divselect::Div8),
47            16 => Some(Divselect::Div16),
48            32 => Some(Divselect::Div32),
49            64 => Some(Divselect::Div64),
50            128 => Some(Divselect::Div128),
51            _ => None,
52        }
53    }
54    #[doc = "Divide by 1"]
55    #[inline(always)]
56    pub fn is_div1(&self) -> bool {
57        *self == Divselect::Div1
58    }
59    #[doc = "Divide by 2"]
60    #[inline(always)]
61    pub fn is_div2(&self) -> bool {
62        *self == Divselect::Div2
63    }
64    #[doc = "Divide by 4"]
65    #[inline(always)]
66    pub fn is_div4(&self) -> bool {
67        *self == Divselect::Div4
68    }
69    #[doc = "Divide by 8"]
70    #[inline(always)]
71    pub fn is_div8(&self) -> bool {
72        *self == Divselect::Div8
73    }
74    #[doc = "Divide by 16"]
75    #[inline(always)]
76    pub fn is_div16(&self) -> bool {
77        *self == Divselect::Div16
78    }
79    #[doc = "Divide by 32"]
80    #[inline(always)]
81    pub fn is_div32(&self) -> bool {
82        *self == Divselect::Div32
83    }
84    #[doc = "Divide by 64"]
85    #[inline(always)]
86    pub fn is_div64(&self) -> bool {
87        *self == Divselect::Div64
88    }
89    #[doc = "Divide by 128"]
90    #[inline(always)]
91    pub fn is_div128(&self) -> bool {
92        *self == Divselect::Div128
93    }
94}
95#[doc = "Field `DIV` writer - Low-Power Clock Division Factor"]
96pub type DivW<'a, REG> = crate::FieldWriter<'a, REG, 8, Divselect>;
97impl<'a, REG> DivW<'a, REG>
98where
99    REG: crate::Writable + crate::RegisterSpec,
100    REG::Ux: From<u8>,
101{
102    #[doc = "Divide by 1"]
103    #[inline(always)]
104    pub fn div1(self) -> &'a mut crate::W<REG> {
105        self.variant(Divselect::Div1)
106    }
107    #[doc = "Divide by 2"]
108    #[inline(always)]
109    pub fn div2(self) -> &'a mut crate::W<REG> {
110        self.variant(Divselect::Div2)
111    }
112    #[doc = "Divide by 4"]
113    #[inline(always)]
114    pub fn div4(self) -> &'a mut crate::W<REG> {
115        self.variant(Divselect::Div4)
116    }
117    #[doc = "Divide by 8"]
118    #[inline(always)]
119    pub fn div8(self) -> &'a mut crate::W<REG> {
120        self.variant(Divselect::Div8)
121    }
122    #[doc = "Divide by 16"]
123    #[inline(always)]
124    pub fn div16(self) -> &'a mut crate::W<REG> {
125        self.variant(Divselect::Div16)
126    }
127    #[doc = "Divide by 32"]
128    #[inline(always)]
129    pub fn div32(self) -> &'a mut crate::W<REG> {
130        self.variant(Divselect::Div32)
131    }
132    #[doc = "Divide by 64"]
133    #[inline(always)]
134    pub fn div64(self) -> &'a mut crate::W<REG> {
135        self.variant(Divselect::Div64)
136    }
137    #[doc = "Divide by 128"]
138    #[inline(always)]
139    pub fn div128(self) -> &'a mut crate::W<REG> {
140        self.variant(Divselect::Div128)
141    }
142}
143impl R {
144    #[doc = "Bits 0:7 - Low-Power Clock Division Factor"]
145    #[inline(always)]
146    pub fn div(&self) -> DivR {
147        DivR::new(self.bits)
148    }
149}
150impl W {
151    #[doc = "Bits 0:7 - Low-Power Clock Division Factor"]
152    #[inline(always)]
153    #[must_use]
154    pub fn div(&mut self) -> DivW<CpudivSpec> {
155        DivW::new(self, 0)
156    }
157}
158#[doc = "CPU Clock Division\n\nYou can [`read`](crate::Reg::read) this register and get [`cpudiv::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cpudiv::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
159pub struct CpudivSpec;
160impl crate::RegisterSpec for CpudivSpec {
161    type Ux = u8;
162}
163#[doc = "`read()` method returns [`cpudiv::R`](R) reader structure"]
164impl crate::Readable for CpudivSpec {}
165#[doc = "`write(|w| ..)` method takes [`cpudiv::W`](W) writer structure"]
166impl crate::Writable for CpudivSpec {
167    type Safety = crate::Unsafe;
168    const ZERO_TO_MODIFY_FIELDS_BITMAP: u8 = 0;
169    const ONE_TO_MODIFY_FIELDS_BITMAP: u8 = 0;
170}
171#[doc = "`reset()` method sets CPUDIV to value 0x01"]
172impl crate::Resettable for CpudivSpec {
173    const RESET_VALUE: u8 = 0x01;
174}
atsamd51n/mclk/cpudiv.rs

atsamd51n/mclk/
cpudiv.rs
