1#[doc = "Register `CTRLA` reader"]
2pub type R = crate::R<CtrlaSpec>;
3#[doc = "Register `CTRLA` writer"]
4pub type W = crate::W<CtrlaSpec>;
5#[doc = "Field `SWRST` reader - Software Reset"]
6pub type SwrstR = crate::BitReader;
7#[doc = "Field `SWRST` writer - Software Reset"]
8pub type SwrstW<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `ENABLE` reader - Enable"]
10pub type EnableR = crate::BitReader;
11#[doc = "Field `ENABLE` writer - Enable"]
12pub type EnableW<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Operating Mode\n\nValue on reset: 0"]
14#[derive(Clone, Copy, Debug, PartialEq, Eq)]
15#[repr(u8)]
16pub enum Modeselect {
17 #[doc = "0: USART with external clock"]
18 UsartExtClk = 0,
19 #[doc = "1: USART with internal clock"]
20 UsartIntClk = 1,
21 #[doc = "2: SPI in slave operation"]
22 SpiSlave = 2,
23 #[doc = "3: SPI in master operation"]
24 SpiMaster = 3,
25 #[doc = "4: I2C slave operation"]
26 I2cSlave = 4,
27 #[doc = "5: I2C master operation"]
28 I2cMaster = 5,
29}
30impl From<Modeselect> for u8 {
31 #[inline(always)]
32 fn from(variant: Modeselect) -> Self {
33 variant as _
34 }
35}
36impl crate::FieldSpec for Modeselect {
37 type Ux = u8;
38}
39impl crate::IsEnum for Modeselect {}
40#[doc = "Field `MODE` reader - Operating Mode"]
41pub type ModeR = crate::FieldReader<Modeselect>;
42impl ModeR {
43 #[doc = "Get enumerated values variant"]
44 #[inline(always)]
45 pub const fn variant(&self) -> Option<Modeselect> {
46 match self.bits {
47 0 => Some(Modeselect::UsartExtClk),
48 1 => Some(Modeselect::UsartIntClk),
49 2 => Some(Modeselect::SpiSlave),
50 3 => Some(Modeselect::SpiMaster),
51 4 => Some(Modeselect::I2cSlave),
52 5 => Some(Modeselect::I2cMaster),
53 _ => None,
54 }
55 }
56 #[doc = "USART with external clock"]
57 #[inline(always)]
58 pub fn is_usart_ext_clk(&self) -> bool {
59 *self == Modeselect::UsartExtClk
60 }
61 #[doc = "USART with internal clock"]
62 #[inline(always)]
63 pub fn is_usart_int_clk(&self) -> bool {
64 *self == Modeselect::UsartIntClk
65 }
66 #[doc = "SPI in slave operation"]
67 #[inline(always)]
68 pub fn is_spi_slave(&self) -> bool {
69 *self == Modeselect::SpiSlave
70 }
71 #[doc = "SPI in master operation"]
72 #[inline(always)]
73 pub fn is_spi_master(&self) -> bool {
74 *self == Modeselect::SpiMaster
75 }
76 #[doc = "I2C slave operation"]
77 #[inline(always)]
78 pub fn is_i2c_slave(&self) -> bool {
79 *self == Modeselect::I2cSlave
80 }
81 #[doc = "I2C master operation"]
82 #[inline(always)]
83 pub fn is_i2c_master(&self) -> bool {
84 *self == Modeselect::I2cMaster
85 }
86}
87#[doc = "Field `MODE` writer - Operating Mode"]
88pub type ModeW<'a, REG> = crate::FieldWriter<'a, REG, 3, Modeselect>;
89impl<'a, REG> ModeW<'a, REG>
90where
91 REG: crate::Writable + crate::RegisterSpec,
92 REG::Ux: From<u8>,
93{
94 #[doc = "USART with external clock"]
95 #[inline(always)]
96 pub fn usart_ext_clk(self) -> &'a mut crate::W<REG> {
97 self.variant(Modeselect::UsartExtClk)
98 }
99 #[doc = "USART with internal clock"]
100 #[inline(always)]
101 pub fn usart_int_clk(self) -> &'a mut crate::W<REG> {
102 self.variant(Modeselect::UsartIntClk)
103 }
104 #[doc = "SPI in slave operation"]
105 #[inline(always)]
106 pub fn spi_slave(self) -> &'a mut crate::W<REG> {
107 self.variant(Modeselect::SpiSlave)
108 }
109 #[doc = "SPI in master operation"]
110 #[inline(always)]
111 pub fn spi_master(self) -> &'a mut crate::W<REG> {
112 self.variant(Modeselect::SpiMaster)
113 }
114 #[doc = "I2C slave operation"]
115 #[inline(always)]
116 pub fn i2c_slave(self) -> &'a mut crate::W<REG> {
117 self.variant(Modeselect::I2cSlave)
118 }
119 #[doc = "I2C master operation"]
120 #[inline(always)]
121 pub fn i2c_master(self) -> &'a mut crate::W<REG> {
122 self.variant(Modeselect::I2cMaster)
123 }
124}
125#[doc = "Field `RUNSTDBY` reader - Run during Standby"]
126pub type RunstdbyR = crate::BitReader;
127#[doc = "Field `RUNSTDBY` writer - Run during Standby"]
128pub type RunstdbyW<'a, REG> = crate::BitWriter<'a, REG>;
129#[doc = "Field `PINOUT` reader - Pin Usage"]
130pub type PinoutR = crate::BitReader;
131#[doc = "Field `PINOUT` writer - Pin Usage"]
132pub type PinoutW<'a, REG> = crate::BitWriter<'a, REG>;
133#[doc = "SDA Hold Time\n\nValue on reset: 0"]
134#[derive(Clone, Copy, Debug, PartialEq, Eq)]
135#[repr(u8)]
136pub enum Sdaholdselect {
137 #[doc = "0: Disabled"]
138 Disable = 0,
139 #[doc = "1: 50-100ns hold time"]
140 _75ns = 1,
141 #[doc = "2: 300-600ns hold time"]
142 _450ns = 2,
143 #[doc = "3: 400-800ns hold time"]
144 _600ns = 3,
145}
146impl From<Sdaholdselect> for u8 {
147 #[inline(always)]
148 fn from(variant: Sdaholdselect) -> Self {
149 variant as _
150 }
151}
152impl crate::FieldSpec for Sdaholdselect {
153 type Ux = u8;
154}
155impl crate::IsEnum for Sdaholdselect {}
156#[doc = "Field `SDAHOLD` reader - SDA Hold Time"]
157pub type SdaholdR = crate::FieldReader<Sdaholdselect>;
158impl SdaholdR {
159 #[doc = "Get enumerated values variant"]
160 #[inline(always)]
161 pub const fn variant(&self) -> Sdaholdselect {
162 match self.bits {
163 0 => Sdaholdselect::Disable,
164 1 => Sdaholdselect::_75ns,
165 2 => Sdaholdselect::_450ns,
166 3 => Sdaholdselect::_600ns,
167 _ => unreachable!(),
168 }
169 }
170 #[doc = "Disabled"]
171 #[inline(always)]
172 pub fn is_disable(&self) -> bool {
173 *self == Sdaholdselect::Disable
174 }
175 #[doc = "50-100ns hold time"]
176 #[inline(always)]
177 pub fn is_75ns(&self) -> bool {
178 *self == Sdaholdselect::_75ns
179 }
180 #[doc = "300-600ns hold time"]
181 #[inline(always)]
182 pub fn is_450ns(&self) -> bool {
183 *self == Sdaholdselect::_450ns
184 }
185 #[doc = "400-800ns hold time"]
186 #[inline(always)]
187 pub fn is_600ns(&self) -> bool {
188 *self == Sdaholdselect::_600ns
189 }
190}
191#[doc = "Field `SDAHOLD` writer - SDA Hold Time"]
192pub type SdaholdW<'a, REG> = crate::FieldWriter<'a, REG, 2, Sdaholdselect, crate::Safe>;
193impl<'a, REG> SdaholdW<'a, REG>
194where
195 REG: crate::Writable + crate::RegisterSpec,
196 REG::Ux: From<u8>,
197{
198 #[doc = "Disabled"]
199 #[inline(always)]
200 pub fn disable(self) -> &'a mut crate::W<REG> {
201 self.variant(Sdaholdselect::Disable)
202 }
203 #[doc = "50-100ns hold time"]
204 #[inline(always)]
205 pub fn _75ns(self) -> &'a mut crate::W<REG> {
206 self.variant(Sdaholdselect::_75ns)
207 }
208 #[doc = "300-600ns hold time"]
209 #[inline(always)]
210 pub fn _450ns(self) -> &'a mut crate::W<REG> {
211 self.variant(Sdaholdselect::_450ns)
212 }
213 #[doc = "400-800ns hold time"]
214 #[inline(always)]
215 pub fn _600ns(self) -> &'a mut crate::W<REG> {
216 self.variant(Sdaholdselect::_600ns)
217 }
218}
219#[doc = "Field `SEXTTOEN` reader - Slave SCL Low Extend Timeout"]
220pub type SexttoenR = crate::BitReader;
221#[doc = "Field `SEXTTOEN` writer - Slave SCL Low Extend Timeout"]
222pub type SexttoenW<'a, REG> = crate::BitWriter<'a, REG>;
223#[doc = "Transfer Speed\n\nValue on reset: 0"]
224#[derive(Clone, Copy, Debug, PartialEq, Eq)]
225#[repr(u8)]
226pub enum Speedselect {
227 #[doc = "0: Standard Mode(Sm) Upto 100kHz and Fast Mode(Fm) Upto 400kHz"]
228 StandardAndFastMode = 0,
229 #[doc = "1: Fast-mode Plus Upto 1MHz"]
230 FastplusMode = 1,
231 #[doc = "2: High-speed mode Upto 3.4MHz"]
232 HighSpeedMode = 2,
233}
234impl From<Speedselect> for u8 {
235 #[inline(always)]
236 fn from(variant: Speedselect) -> Self {
237 variant as _
238 }
239}
240impl crate::FieldSpec for Speedselect {
241 type Ux = u8;
242}
243impl crate::IsEnum for Speedselect {}
244#[doc = "Field `SPEED` reader - Transfer Speed"]
245pub type SpeedR = crate::FieldReader<Speedselect>;
246impl SpeedR {
247 #[doc = "Get enumerated values variant"]
248 #[inline(always)]
249 pub const fn variant(&self) -> Option<Speedselect> {
250 match self.bits {
251 0 => Some(Speedselect::StandardAndFastMode),
252 1 => Some(Speedselect::FastplusMode),
253 2 => Some(Speedselect::HighSpeedMode),
254 _ => None,
255 }
256 }
257 #[doc = "Standard Mode(Sm) Upto 100kHz and Fast Mode(Fm) Upto 400kHz"]
258 #[inline(always)]
259 pub fn is_standard_and_fast_mode(&self) -> bool {
260 *self == Speedselect::StandardAndFastMode
261 }
262 #[doc = "Fast-mode Plus Upto 1MHz"]
263 #[inline(always)]
264 pub fn is_fastplus_mode(&self) -> bool {
265 *self == Speedselect::FastplusMode
266 }
267 #[doc = "High-speed mode Upto 3.4MHz"]
268 #[inline(always)]
269 pub fn is_high_speed_mode(&self) -> bool {
270 *self == Speedselect::HighSpeedMode
271 }
272}
273#[doc = "Field `SPEED` writer - Transfer Speed"]
274pub type SpeedW<'a, REG> = crate::FieldWriter<'a, REG, 2, Speedselect>;
275impl<'a, REG> SpeedW<'a, REG>
276where
277 REG: crate::Writable + crate::RegisterSpec,
278 REG::Ux: From<u8>,
279{
280 #[doc = "Standard Mode(Sm) Upto 100kHz and Fast Mode(Fm) Upto 400kHz"]
281 #[inline(always)]
282 pub fn standard_and_fast_mode(self) -> &'a mut crate::W<REG> {
283 self.variant(Speedselect::StandardAndFastMode)
284 }
285 #[doc = "Fast-mode Plus Upto 1MHz"]
286 #[inline(always)]
287 pub fn fastplus_mode(self) -> &'a mut crate::W<REG> {
288 self.variant(Speedselect::FastplusMode)
289 }
290 #[doc = "High-speed mode Upto 3.4MHz"]
291 #[inline(always)]
292 pub fn high_speed_mode(self) -> &'a mut crate::W<REG> {
293 self.variant(Speedselect::HighSpeedMode)
294 }
295}
296#[doc = "Field `SCLSM` reader - SCL Clock Stretch Mode"]
297pub type SclsmR = crate::BitReader;
298#[doc = "Field `SCLSM` writer - SCL Clock Stretch Mode"]
299pub type SclsmW<'a, REG> = crate::BitWriter<'a, REG>;
300#[doc = "Field `LOWTOUTEN` reader - SCL Low Timeout Enable"]
301pub type LowtoutenR = crate::BitReader;
302#[doc = "Field `LOWTOUTEN` writer - SCL Low Timeout Enable"]
303pub type LowtoutenW<'a, REG> = crate::BitWriter<'a, REG>;
304impl R {
305 #[doc = "Bit 0 - Software Reset"]
306 #[inline(always)]
307 pub fn swrst(&self) -> SwrstR {
308 SwrstR::new((self.bits & 1) != 0)
309 }
310 #[doc = "Bit 1 - Enable"]
311 #[inline(always)]
312 pub fn enable(&self) -> EnableR {
313 EnableR::new(((self.bits >> 1) & 1) != 0)
314 }
315 #[doc = "Bits 2:4 - Operating Mode"]
316 #[inline(always)]
317 pub fn mode(&self) -> ModeR {
318 ModeR::new(((self.bits >> 2) & 7) as u8)
319 }
320 #[doc = "Bit 7 - Run during Standby"]
321 #[inline(always)]
322 pub fn runstdby(&self) -> RunstdbyR {
323 RunstdbyR::new(((self.bits >> 7) & 1) != 0)
324 }
325 #[doc = "Bit 16 - Pin Usage"]
326 #[inline(always)]
327 pub fn pinout(&self) -> PinoutR {
328 PinoutR::new(((self.bits >> 16) & 1) != 0)
329 }
330 #[doc = "Bits 20:21 - SDA Hold Time"]
331 #[inline(always)]
332 pub fn sdahold(&self) -> SdaholdR {
333 SdaholdR::new(((self.bits >> 20) & 3) as u8)
334 }
335 #[doc = "Bit 23 - Slave SCL Low Extend Timeout"]
336 #[inline(always)]
337 pub fn sexttoen(&self) -> SexttoenR {
338 SexttoenR::new(((self.bits >> 23) & 1) != 0)
339 }
340 #[doc = "Bits 24:25 - Transfer Speed"]
341 #[inline(always)]
342 pub fn speed(&self) -> SpeedR {
343 SpeedR::new(((self.bits >> 24) & 3) as u8)
344 }
345 #[doc = "Bit 27 - SCL Clock Stretch Mode"]
346 #[inline(always)]
347 pub fn sclsm(&self) -> SclsmR {
348 SclsmR::new(((self.bits >> 27) & 1) != 0)
349 }
350 #[doc = "Bit 30 - SCL Low Timeout Enable"]
351 #[inline(always)]
352 pub fn lowtouten(&self) -> LowtoutenR {
353 LowtoutenR::new(((self.bits >> 30) & 1) != 0)
354 }
355}
356impl W {
357 #[doc = "Bit 0 - Software Reset"]
358 #[inline(always)]
359 #[must_use]
360 pub fn swrst(&mut self) -> SwrstW<CtrlaSpec> {
361 SwrstW::new(self, 0)
362 }
363 #[doc = "Bit 1 - Enable"]
364 #[inline(always)]
365 #[must_use]
366 pub fn enable(&mut self) -> EnableW<CtrlaSpec> {
367 EnableW::new(self, 1)
368 }
369 #[doc = "Bits 2:4 - Operating Mode"]
370 #[inline(always)]
371 #[must_use]
372 pub fn mode(&mut self) -> ModeW<CtrlaSpec> {
373 ModeW::new(self, 2)
374 }
375 #[doc = "Bit 7 - Run during Standby"]
376 #[inline(always)]
377 #[must_use]
378 pub fn runstdby(&mut self) -> RunstdbyW<CtrlaSpec> {
379 RunstdbyW::new(self, 7)
380 }
381 #[doc = "Bit 16 - Pin Usage"]
382 #[inline(always)]
383 #[must_use]
384 pub fn pinout(&mut self) -> PinoutW<CtrlaSpec> {
385 PinoutW::new(self, 16)
386 }
387 #[doc = "Bits 20:21 - SDA Hold Time"]
388 #[inline(always)]
389 #[must_use]
390 pub fn sdahold(&mut self) -> SdaholdW<CtrlaSpec> {
391 SdaholdW::new(self, 20)
392 }
393 #[doc = "Bit 23 - Slave SCL Low Extend Timeout"]
394 #[inline(always)]
395 #[must_use]
396 pub fn sexttoen(&mut self) -> SexttoenW<CtrlaSpec> {
397 SexttoenW::new(self, 23)
398 }
399 #[doc = "Bits 24:25 - Transfer Speed"]
400 #[inline(always)]
401 #[must_use]
402 pub fn speed(&mut self) -> SpeedW<CtrlaSpec> {
403 SpeedW::new(self, 24)
404 }
405 #[doc = "Bit 27 - SCL Clock Stretch Mode"]
406 #[inline(always)]
407 #[must_use]
408 pub fn sclsm(&mut self) -> SclsmW<CtrlaSpec> {
409 SclsmW::new(self, 27)
410 }
411 #[doc = "Bit 30 - SCL Low Timeout Enable"]
412 #[inline(always)]
413 #[must_use]
414 pub fn lowtouten(&mut self) -> LowtoutenW<CtrlaSpec> {
415 LowtoutenW::new(self, 30)
416 }
417}
418#[doc = "I2CS Control A\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrla::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrla::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
419pub struct CtrlaSpec;
420impl crate::RegisterSpec for CtrlaSpec {
421 type Ux = u32;
422}
423#[doc = "`read()` method returns [`ctrla::R`](R) reader structure"]
424impl crate::Readable for CtrlaSpec {}
425#[doc = "`write(|w| ..)` method takes [`ctrla::W`](W) writer structure"]
426impl crate::Writable for CtrlaSpec {
427 type Safety = crate::Unsafe;
428 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
429 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
430}
431#[doc = "`reset()` method sets CTRLA to value 0"]
432impl crate::Resettable for CtrlaSpec {
433 const RESET_VALUE: u32 = 0;
434}