atsamd51n/etm/
cr.rs

1#[doc = "Register `CR` reader"]
2pub type R = crate::R<CrSpec>;
3#[doc = "Register `CR` writer"]
4pub type W = crate::W<CrSpec>;
5#[doc = "Field `ETMPD` reader - ETM Power Down"]
6pub type EtmpdR = crate::BitReader;
7#[doc = "Field `ETMPD` writer - ETM Power Down"]
8pub type EtmpdW<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `PORTSIZE` reader - Port Size bits 2:0"]
10pub type PortsizeR = crate::FieldReader;
11#[doc = "Field `PORTSIZE` writer - Port Size bits 2:0"]
12pub type PortsizeW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
13#[doc = "Field `STALL` reader - Stall Processor"]
14pub type StallR = crate::BitReader;
15#[doc = "Field `STALL` writer - Stall Processor"]
16pub type StallW<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `BROUT` reader - Branch Output"]
18pub type BroutR = crate::BitReader;
19#[doc = "Field `BROUT` writer - Branch Output"]
20pub type BroutW<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `DBGRQ` reader - Debug Request Control"]
22pub type DbgrqR = crate::BitReader;
23#[doc = "Field `DBGRQ` writer - Debug Request Control"]
24pub type DbgrqW<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `PROG` reader - ETM Programming"]
26pub type ProgR = crate::BitReader;
27#[doc = "Field `PROG` writer - ETM Programming"]
28pub type ProgW<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `PORTSEL` reader - ETM Port Select"]
30pub type PortselR = crate::BitReader;
31#[doc = "Field `PORTSEL` writer - ETM Port Select"]
32pub type PortselW<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `PORTMODE2` reader - Port Mode bit 2"]
34pub type Portmode2R = crate::BitReader;
35#[doc = "Field `PORTMODE2` writer - Port Mode bit 2"]
36pub type Portmode2W<'a, REG> = crate::BitWriter<'a, REG>;
37#[doc = "Field `PORTMODE` reader - Port Mode bits 1:0"]
38pub type PortmodeR = crate::FieldReader;
39#[doc = "Field `PORTMODE` writer - Port Mode bits 1:0"]
40pub type PortmodeW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
41#[doc = "Field `PORTSIZE3` reader - Port Size bit 3"]
42pub type Portsize3R = crate::BitReader;
43#[doc = "Field `PORTSIZE3` writer - Port Size bit 3"]
44pub type Portsize3W<'a, REG> = crate::BitWriter<'a, REG>;
45#[doc = "Field `TSEN` reader - TimeStamp Enable"]
46pub type TsenR = crate::BitReader;
47#[doc = "Field `TSEN` writer - TimeStamp Enable"]
48pub type TsenW<'a, REG> = crate::BitWriter<'a, REG>;
49impl R {
50    #[doc = "Bit 0 - ETM Power Down"]
51    #[inline(always)]
52    pub fn etmpd(&self) -> EtmpdR {
53        EtmpdR::new((self.bits & 1) != 0)
54    }
55    #[doc = "Bits 4:6 - Port Size bits 2:0"]
56    #[inline(always)]
57    pub fn portsize(&self) -> PortsizeR {
58        PortsizeR::new(((self.bits >> 4) & 7) as u8)
59    }
60    #[doc = "Bit 7 - Stall Processor"]
61    #[inline(always)]
62    pub fn stall(&self) -> StallR {
63        StallR::new(((self.bits >> 7) & 1) != 0)
64    }
65    #[doc = "Bit 8 - Branch Output"]
66    #[inline(always)]
67    pub fn brout(&self) -> BroutR {
68        BroutR::new(((self.bits >> 8) & 1) != 0)
69    }
70    #[doc = "Bit 9 - Debug Request Control"]
71    #[inline(always)]
72    pub fn dbgrq(&self) -> DbgrqR {
73        DbgrqR::new(((self.bits >> 9) & 1) != 0)
74    }
75    #[doc = "Bit 10 - ETM Programming"]
76    #[inline(always)]
77    pub fn prog(&self) -> ProgR {
78        ProgR::new(((self.bits >> 10) & 1) != 0)
79    }
80    #[doc = "Bit 11 - ETM Port Select"]
81    #[inline(always)]
82    pub fn portsel(&self) -> PortselR {
83        PortselR::new(((self.bits >> 11) & 1) != 0)
84    }
85    #[doc = "Bit 13 - Port Mode bit 2"]
86    #[inline(always)]
87    pub fn portmode2(&self) -> Portmode2R {
88        Portmode2R::new(((self.bits >> 13) & 1) != 0)
89    }
90    #[doc = "Bits 16:17 - Port Mode bits 1:0"]
91    #[inline(always)]
92    pub fn portmode(&self) -> PortmodeR {
93        PortmodeR::new(((self.bits >> 16) & 3) as u8)
94    }
95    #[doc = "Bit 21 - Port Size bit 3"]
96    #[inline(always)]
97    pub fn portsize3(&self) -> Portsize3R {
98        Portsize3R::new(((self.bits >> 21) & 1) != 0)
99    }
100    #[doc = "Bit 28 - TimeStamp Enable"]
101    #[inline(always)]
102    pub fn tsen(&self) -> TsenR {
103        TsenR::new(((self.bits >> 28) & 1) != 0)
104    }
105}
106impl W {
107    #[doc = "Bit 0 - ETM Power Down"]
108    #[inline(always)]
109    #[must_use]
110    pub fn etmpd(&mut self) -> EtmpdW<CrSpec> {
111        EtmpdW::new(self, 0)
112    }
113    #[doc = "Bits 4:6 - Port Size bits 2:0"]
114    #[inline(always)]
115    #[must_use]
116    pub fn portsize(&mut self) -> PortsizeW<CrSpec> {
117        PortsizeW::new(self, 4)
118    }
119    #[doc = "Bit 7 - Stall Processor"]
120    #[inline(always)]
121    #[must_use]
122    pub fn stall(&mut self) -> StallW<CrSpec> {
123        StallW::new(self, 7)
124    }
125    #[doc = "Bit 8 - Branch Output"]
126    #[inline(always)]
127    #[must_use]
128    pub fn brout(&mut self) -> BroutW<CrSpec> {
129        BroutW::new(self, 8)
130    }
131    #[doc = "Bit 9 - Debug Request Control"]
132    #[inline(always)]
133    #[must_use]
134    pub fn dbgrq(&mut self) -> DbgrqW<CrSpec> {
135        DbgrqW::new(self, 9)
136    }
137    #[doc = "Bit 10 - ETM Programming"]
138    #[inline(always)]
139    #[must_use]
140    pub fn prog(&mut self) -> ProgW<CrSpec> {
141        ProgW::new(self, 10)
142    }
143    #[doc = "Bit 11 - ETM Port Select"]
144    #[inline(always)]
145    #[must_use]
146    pub fn portsel(&mut self) -> PortselW<CrSpec> {
147        PortselW::new(self, 11)
148    }
149    #[doc = "Bit 13 - Port Mode bit 2"]
150    #[inline(always)]
151    #[must_use]
152    pub fn portmode2(&mut self) -> Portmode2W<CrSpec> {
153        Portmode2W::new(self, 13)
154    }
155    #[doc = "Bits 16:17 - Port Mode bits 1:0"]
156    #[inline(always)]
157    #[must_use]
158    pub fn portmode(&mut self) -> PortmodeW<CrSpec> {
159        PortmodeW::new(self, 16)
160    }
161    #[doc = "Bit 21 - Port Size bit 3"]
162    #[inline(always)]
163    #[must_use]
164    pub fn portsize3(&mut self) -> Portsize3W<CrSpec> {
165        Portsize3W::new(self, 21)
166    }
167    #[doc = "Bit 28 - TimeStamp Enable"]
168    #[inline(always)]
169    #[must_use]
170    pub fn tsen(&mut self) -> TsenW<CrSpec> {
171        TsenW::new(self, 28)
172    }
173}
174#[doc = "ETM Main Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
175pub struct CrSpec;
176impl crate::RegisterSpec for CrSpec {
177    type Ux = u32;
178}
179#[doc = "`read()` method returns [`cr::R`](R) reader structure"]
180impl crate::Readable for CrSpec {}
181#[doc = "`write(|w| ..)` method takes [`cr::W`](W) writer structure"]
182impl crate::Writable for CrSpec {
183    type Safety = crate::Unsafe;
184    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
185    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
186}
187#[doc = "`reset()` method sets CR to value 0x0411"]
188impl crate::Resettable for CrSpec {
189    const RESET_VALUE: u32 = 0x0411;
190}
atsamd51n/etm/cr.rs

atsamd51n/etm/
cr.rs
