atsamd51n/dac/
intenclr.rs

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1#[doc = "Register `INTENCLR` reader"]
2pub type R = crate::R<IntenclrSpec>;
3#[doc = "Register `INTENCLR` writer"]
4pub type W = crate::W<IntenclrSpec>;
5#[doc = "Field `UNDERRUN0` reader - Underrun 0 Interrupt Enable"]
6pub type Underrun0R = crate::BitReader;
7#[doc = "Field `UNDERRUN0` writer - Underrun 0 Interrupt Enable"]
8pub type Underrun0W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `UNDERRUN1` reader - Underrun 1 Interrupt Enable"]
10pub type Underrun1R = crate::BitReader;
11#[doc = "Field `UNDERRUN1` writer - Underrun 1 Interrupt Enable"]
12pub type Underrun1W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `EMPTY0` reader - Data Buffer 0 Empty Interrupt Enable"]
14pub type Empty0R = crate::BitReader;
15#[doc = "Field `EMPTY0` writer - Data Buffer 0 Empty Interrupt Enable"]
16pub type Empty0W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `EMPTY1` reader - Data Buffer 1 Empty Interrupt Enable"]
18pub type Empty1R = crate::BitReader;
19#[doc = "Field `EMPTY1` writer - Data Buffer 1 Empty Interrupt Enable"]
20pub type Empty1W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `RESRDY0` reader - Result 0 Ready Interrupt Enable"]
22pub type Resrdy0R = crate::BitReader;
23#[doc = "Field `RESRDY0` writer - Result 0 Ready Interrupt Enable"]
24pub type Resrdy0W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `RESRDY1` reader - Result 1 Ready Interrupt Enable"]
26pub type Resrdy1R = crate::BitReader;
27#[doc = "Field `RESRDY1` writer - Result 1 Ready Interrupt Enable"]
28pub type Resrdy1W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `OVERRUN0` reader - Overrun 0 Interrupt Enable"]
30pub type Overrun0R = crate::BitReader;
31#[doc = "Field `OVERRUN0` writer - Overrun 0 Interrupt Enable"]
32pub type Overrun0W<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `OVERRUN1` reader - Overrun 1 Interrupt Enable"]
34pub type Overrun1R = crate::BitReader;
35#[doc = "Field `OVERRUN1` writer - Overrun 1 Interrupt Enable"]
36pub type Overrun1W<'a, REG> = crate::BitWriter<'a, REG>;
37impl R {
38    #[doc = "Bit 0 - Underrun 0 Interrupt Enable"]
39    #[inline(always)]
40    pub fn underrun0(&self) -> Underrun0R {
41        Underrun0R::new((self.bits & 1) != 0)
42    }
43    #[doc = "Bit 1 - Underrun 1 Interrupt Enable"]
44    #[inline(always)]
45    pub fn underrun1(&self) -> Underrun1R {
46        Underrun1R::new(((self.bits >> 1) & 1) != 0)
47    }
48    #[doc = "Bit 2 - Data Buffer 0 Empty Interrupt Enable"]
49    #[inline(always)]
50    pub fn empty0(&self) -> Empty0R {
51        Empty0R::new(((self.bits >> 2) & 1) != 0)
52    }
53    #[doc = "Bit 3 - Data Buffer 1 Empty Interrupt Enable"]
54    #[inline(always)]
55    pub fn empty1(&self) -> Empty1R {
56        Empty1R::new(((self.bits >> 3) & 1) != 0)
57    }
58    #[doc = "Bit 4 - Result 0 Ready Interrupt Enable"]
59    #[inline(always)]
60    pub fn resrdy0(&self) -> Resrdy0R {
61        Resrdy0R::new(((self.bits >> 4) & 1) != 0)
62    }
63    #[doc = "Bit 5 - Result 1 Ready Interrupt Enable"]
64    #[inline(always)]
65    pub fn resrdy1(&self) -> Resrdy1R {
66        Resrdy1R::new(((self.bits >> 5) & 1) != 0)
67    }
68    #[doc = "Bit 6 - Overrun 0 Interrupt Enable"]
69    #[inline(always)]
70    pub fn overrun0(&self) -> Overrun0R {
71        Overrun0R::new(((self.bits >> 6) & 1) != 0)
72    }
73    #[doc = "Bit 7 - Overrun 1 Interrupt Enable"]
74    #[inline(always)]
75    pub fn overrun1(&self) -> Overrun1R {
76        Overrun1R::new(((self.bits >> 7) & 1) != 0)
77    }
78}
79impl W {
80    #[doc = "Bit 0 - Underrun 0 Interrupt Enable"]
81    #[inline(always)]
82    #[must_use]
83    pub fn underrun0(&mut self) -> Underrun0W<IntenclrSpec> {
84        Underrun0W::new(self, 0)
85    }
86    #[doc = "Bit 1 - Underrun 1 Interrupt Enable"]
87    #[inline(always)]
88    #[must_use]
89    pub fn underrun1(&mut self) -> Underrun1W<IntenclrSpec> {
90        Underrun1W::new(self, 1)
91    }
92    #[doc = "Bit 2 - Data Buffer 0 Empty Interrupt Enable"]
93    #[inline(always)]
94    #[must_use]
95    pub fn empty0(&mut self) -> Empty0W<IntenclrSpec> {
96        Empty0W::new(self, 2)
97    }
98    #[doc = "Bit 3 - Data Buffer 1 Empty Interrupt Enable"]
99    #[inline(always)]
100    #[must_use]
101    pub fn empty1(&mut self) -> Empty1W<IntenclrSpec> {
102        Empty1W::new(self, 3)
103    }
104    #[doc = "Bit 4 - Result 0 Ready Interrupt Enable"]
105    #[inline(always)]
106    #[must_use]
107    pub fn resrdy0(&mut self) -> Resrdy0W<IntenclrSpec> {
108        Resrdy0W::new(self, 4)
109    }
110    #[doc = "Bit 5 - Result 1 Ready Interrupt Enable"]
111    #[inline(always)]
112    #[must_use]
113    pub fn resrdy1(&mut self) -> Resrdy1W<IntenclrSpec> {
114        Resrdy1W::new(self, 5)
115    }
116    #[doc = "Bit 6 - Overrun 0 Interrupt Enable"]
117    #[inline(always)]
118    #[must_use]
119    pub fn overrun0(&mut self) -> Overrun0W<IntenclrSpec> {
120        Overrun0W::new(self, 6)
121    }
122    #[doc = "Bit 7 - Overrun 1 Interrupt Enable"]
123    #[inline(always)]
124    #[must_use]
125    pub fn overrun1(&mut self) -> Overrun1W<IntenclrSpec> {
126        Overrun1W::new(self, 7)
127    }
128}
129#[doc = "Interrupt Enable Clear\n\nYou can [`read`](crate::Reg::read) this register and get [`intenclr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intenclr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
130pub struct IntenclrSpec;
131impl crate::RegisterSpec for IntenclrSpec {
132    type Ux = u8;
133}
134#[doc = "`read()` method returns [`intenclr::R`](R) reader structure"]
135impl crate::Readable for IntenclrSpec {}
136#[doc = "`write(|w| ..)` method takes [`intenclr::W`](W) writer structure"]
137impl crate::Writable for IntenclrSpec {
138    type Safety = crate::Unsafe;
139    const ZERO_TO_MODIFY_FIELDS_BITMAP: u8 = 0;
140    const ONE_TO_MODIFY_FIELDS_BITMAP: u8 = 0;
141}
142#[doc = "`reset()` method sets INTENCLR to value 0"]
143impl crate::Resettable for IntenclrSpec {
144    const RESET_VALUE: u8 = 0;
145}
atsamd51n/dac/intenclr.rs

atsamd51n/dac/
intenclr.rs
