atsamd51n/core_debug/
dhcsr.rs

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1#[doc = "Register `DHCSR` reader"]
2pub type R = crate::R<DhcsrSpec>;
3#[doc = "Register `DHCSR` writer"]
4pub type W = crate::W<DhcsrSpec>;
5#[doc = "Field `C_DEBUGEN` reader - "]
6pub type CDebugenR = crate::BitReader;
7#[doc = "Field `C_DEBUGEN` writer - "]
8pub type CDebugenW<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `C_HALT` reader - "]
10pub type CHaltR = crate::BitReader;
11#[doc = "Field `C_HALT` writer - "]
12pub type CHaltW<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `C_STEP` reader - "]
14pub type CStepR = crate::BitReader;
15#[doc = "Field `C_STEP` writer - "]
16pub type CStepW<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `C_MASKINTS` reader - "]
18pub type CMaskintsR = crate::BitReader;
19#[doc = "Field `C_MASKINTS` writer - "]
20pub type CMaskintsW<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `C_SNAPSTALL` reader - "]
22pub type CSnapstallR = crate::BitReader;
23#[doc = "Field `C_SNAPSTALL` writer - "]
24pub type CSnapstallW<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `S_REGRDY` reader - "]
26pub type SRegrdyR = crate::BitReader;
27#[doc = "Field `DBGKEY` writer - "]
28pub type DbgkeyW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
29#[doc = "Field `S_HALT` reader - "]
30pub type SHaltR = crate::BitReader;
31#[doc = "Field `S_SLEEP` reader - "]
32pub type SSleepR = crate::BitReader;
33#[doc = "Field `S_LOCKUP` reader - "]
34pub type SLockupR = crate::BitReader;
35#[doc = "Field `S_RETIRE_ST` reader - "]
36pub type SRetireStR = crate::BitReader;
37#[doc = "Field `S_RESET_ST` reader - "]
38pub type SResetStR = crate::BitReader;
39impl R {
40    #[doc = "Bit 0"]
41    #[inline(always)]
42    pub fn c_debugen(&self) -> CDebugenR {
43        CDebugenR::new((self.bits & 1) != 0)
44    }
45    #[doc = "Bit 1"]
46    #[inline(always)]
47    pub fn c_halt(&self) -> CHaltR {
48        CHaltR::new(((self.bits >> 1) & 1) != 0)
49    }
50    #[doc = "Bit 2"]
51    #[inline(always)]
52    pub fn c_step(&self) -> CStepR {
53        CStepR::new(((self.bits >> 2) & 1) != 0)
54    }
55    #[doc = "Bit 3"]
56    #[inline(always)]
57    pub fn c_maskints(&self) -> CMaskintsR {
58        CMaskintsR::new(((self.bits >> 3) & 1) != 0)
59    }
60    #[doc = "Bit 5"]
61    #[inline(always)]
62    pub fn c_snapstall(&self) -> CSnapstallR {
63        CSnapstallR::new(((self.bits >> 5) & 1) != 0)
64    }
65    #[doc = "Bit 16"]
66    #[inline(always)]
67    pub fn s_regrdy(&self) -> SRegrdyR {
68        SRegrdyR::new(((self.bits >> 16) & 1) != 0)
69    }
70    #[doc = "Bit 17"]
71    #[inline(always)]
72    pub fn s_halt(&self) -> SHaltR {
73        SHaltR::new(((self.bits >> 17) & 1) != 0)
74    }
75    #[doc = "Bit 18"]
76    #[inline(always)]
77    pub fn s_sleep(&self) -> SSleepR {
78        SSleepR::new(((self.bits >> 18) & 1) != 0)
79    }
80    #[doc = "Bit 19"]
81    #[inline(always)]
82    pub fn s_lockup(&self) -> SLockupR {
83        SLockupR::new(((self.bits >> 19) & 1) != 0)
84    }
85    #[doc = "Bit 24"]
86    #[inline(always)]
87    pub fn s_retire_st(&self) -> SRetireStR {
88        SRetireStR::new(((self.bits >> 24) & 1) != 0)
89    }
90    #[doc = "Bit 25"]
91    #[inline(always)]
92    pub fn s_reset_st(&self) -> SResetStR {
93        SResetStR::new(((self.bits >> 25) & 1) != 0)
94    }
95}
96impl W {
97    #[doc = "Bit 0"]
98    #[inline(always)]
99    #[must_use]
100    pub fn c_debugen(&mut self) -> CDebugenW<DhcsrSpec> {
101        CDebugenW::new(self, 0)
102    }
103    #[doc = "Bit 1"]
104    #[inline(always)]
105    #[must_use]
106    pub fn c_halt(&mut self) -> CHaltW<DhcsrSpec> {
107        CHaltW::new(self, 1)
108    }
109    #[doc = "Bit 2"]
110    #[inline(always)]
111    #[must_use]
112    pub fn c_step(&mut self) -> CStepW<DhcsrSpec> {
113        CStepW::new(self, 2)
114    }
115    #[doc = "Bit 3"]
116    #[inline(always)]
117    #[must_use]
118    pub fn c_maskints(&mut self) -> CMaskintsW<DhcsrSpec> {
119        CMaskintsW::new(self, 3)
120    }
121    #[doc = "Bit 5"]
122    #[inline(always)]
123    #[must_use]
124    pub fn c_snapstall(&mut self) -> CSnapstallW<DhcsrSpec> {
125        CSnapstallW::new(self, 5)
126    }
127    #[doc = "Bits 16:31"]
128    #[inline(always)]
129    #[must_use]
130    pub fn dbgkey(&mut self) -> DbgkeyW<DhcsrSpec> {
131        DbgkeyW::new(self, 16)
132    }
133}
134#[doc = "Debug Halting Control and Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`dhcsr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dhcsr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
135pub struct DhcsrSpec;
136impl crate::RegisterSpec for DhcsrSpec {
137    type Ux = u32;
138}
139#[doc = "`read()` method returns [`dhcsr::R`](R) reader structure"]
140impl crate::Readable for DhcsrSpec {}
141#[doc = "`write(|w| ..)` method takes [`dhcsr::W`](W) writer structure"]
142impl crate::Writable for DhcsrSpec {
143    type Safety = crate::Unsafe;
144    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
145    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
146}
147#[doc = "`reset()` method sets DHCSR to value 0"]
148impl crate::Resettable for DhcsrSpec {
149    const RESET_VALUE: u32 = 0;
150}
atsamd51n/core_debug/dhcsr.rs

atsamd51n/core_debug/
dhcsr.rs
