atsamd51n/evsys/
intpend.rs

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1#[doc = "Register `INTPEND` reader"]
2pub type R = crate::R<IntpendSpec>;
3#[doc = "Register `INTPEND` writer"]
4pub type W = crate::W<IntpendSpec>;
5#[doc = "Field `ID` reader - Channel ID"]
6pub type IdR = crate::FieldReader;
7#[doc = "Field `ID` writer - Channel ID"]
8pub type IdW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
9#[doc = "Field `OVR` reader - Channel Overrun"]
10pub type OvrR = crate::BitReader;
11#[doc = "Field `OVR` writer - Channel Overrun"]
12pub type OvrW<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `EVD` reader - Channel Event Detected"]
14pub type EvdR = crate::BitReader;
15#[doc = "Field `EVD` writer - Channel Event Detected"]
16pub type EvdW<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `READY` reader - Ready"]
18pub type ReadyR = crate::BitReader;
19#[doc = "Field `READY` writer - Ready"]
20pub type ReadyW<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `BUSY` reader - Busy"]
22pub type BusyR = crate::BitReader;
23#[doc = "Field `BUSY` writer - Busy"]
24pub type BusyW<'a, REG> = crate::BitWriter<'a, REG>;
25impl R {
26    #[doc = "Bits 0:3 - Channel ID"]
27    #[inline(always)]
28    pub fn id(&self) -> IdR {
29        IdR::new((self.bits & 0x0f) as u8)
30    }
31    #[doc = "Bit 8 - Channel Overrun"]
32    #[inline(always)]
33    pub fn ovr(&self) -> OvrR {
34        OvrR::new(((self.bits >> 8) & 1) != 0)
35    }
36    #[doc = "Bit 9 - Channel Event Detected"]
37    #[inline(always)]
38    pub fn evd(&self) -> EvdR {
39        EvdR::new(((self.bits >> 9) & 1) != 0)
40    }
41    #[doc = "Bit 14 - Ready"]
42    #[inline(always)]
43    pub fn ready(&self) -> ReadyR {
44        ReadyR::new(((self.bits >> 14) & 1) != 0)
45    }
46    #[doc = "Bit 15 - Busy"]
47    #[inline(always)]
48    pub fn busy(&self) -> BusyR {
49        BusyR::new(((self.bits >> 15) & 1) != 0)
50    }
51}
52impl W {
53    #[doc = "Bits 0:3 - Channel ID"]
54    #[inline(always)]
55    #[must_use]
56    pub fn id(&mut self) -> IdW<IntpendSpec> {
57        IdW::new(self, 0)
58    }
59    #[doc = "Bit 8 - Channel Overrun"]
60    #[inline(always)]
61    #[must_use]
62    pub fn ovr(&mut self) -> OvrW<IntpendSpec> {
63        OvrW::new(self, 8)
64    }
65    #[doc = "Bit 9 - Channel Event Detected"]
66    #[inline(always)]
67    #[must_use]
68    pub fn evd(&mut self) -> EvdW<IntpendSpec> {
69        EvdW::new(self, 9)
70    }
71    #[doc = "Bit 14 - Ready"]
72    #[inline(always)]
73    #[must_use]
74    pub fn ready(&mut self) -> ReadyW<IntpendSpec> {
75        ReadyW::new(self, 14)
76    }
77    #[doc = "Bit 15 - Busy"]
78    #[inline(always)]
79    #[must_use]
80    pub fn busy(&mut self) -> BusyW<IntpendSpec> {
81        BusyW::new(self, 15)
82    }
83}
84#[doc = "Channel Pending Interrupt\n\nYou can [`read`](crate::Reg::read) this register and get [`intpend::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intpend::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
85pub struct IntpendSpec;
86impl crate::RegisterSpec for IntpendSpec {
87    type Ux = u16;
88}
89#[doc = "`read()` method returns [`intpend::R`](R) reader structure"]
90impl crate::Readable for IntpendSpec {}
91#[doc = "`write(|w| ..)` method takes [`intpend::W`](W) writer structure"]
92impl crate::Writable for IntpendSpec {
93    type Safety = crate::Unsafe;
94    const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0;
95    const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0;
96}
97#[doc = "`reset()` method sets INTPEND to value 0x4000"]
98impl crate::Resettable for IntpendSpec {
99    const RESET_VALUE: u16 = 0x4000;
100}
atsamd51n/evsys/intpend.rs

atsamd51n/evsys/
intpend.rs
