atsamd51j/sercom0/i2cm/
status.rs

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1#[doc = "Register `STATUS` reader"]
2pub type R = crate::R<StatusSpec>;
3#[doc = "Register `STATUS` writer"]
4pub type W = crate::W<StatusSpec>;
5#[doc = "Field `BUSERR` reader - Bus Error"]
6pub type BuserrR = crate::BitReader;
7#[doc = "Field `BUSERR` writer - Bus Error"]
8pub type BuserrW<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `ARBLOST` reader - Arbitration Lost"]
10pub type ArblostR = crate::BitReader;
11#[doc = "Field `ARBLOST` writer - Arbitration Lost"]
12pub type ArblostW<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `RXNACK` reader - Received Not Acknowledge"]
14pub type RxnackR = crate::BitReader;
15#[doc = "Field `RXNACK` writer - Received Not Acknowledge"]
16pub type RxnackW<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Bus State\n\nValue on reset: 0"]
18#[derive(Clone, Copy, Debug, PartialEq, Eq)]
19#[repr(u8)]
20pub enum Busstateselect {
21    #[doc = "0: The Bus state is unknown to the I2C Host"]
22    Unknown = 0,
23    #[doc = "1: The Bus state is waiting for a transaction to be initialized"]
24    Idle = 1,
25    #[doc = "2: The I2C Host is the current owner of the bus"]
26    Owner = 2,
27    #[doc = "3: Some other I2C Host owns the bus"]
28    Busy = 3,
29}
30impl From<Busstateselect> for u8 {
31    #[inline(always)]
32    fn from(variant: Busstateselect) -> Self {
33        variant as _
34    }
35}
36impl crate::FieldSpec for Busstateselect {
37    type Ux = u8;
38}
39impl crate::IsEnum for Busstateselect {}
40#[doc = "Field `BUSSTATE` reader - Bus State"]
41pub type BusstateR = crate::FieldReader<Busstateselect>;
42impl BusstateR {
43    #[doc = "Get enumerated values variant"]
44    #[inline(always)]
45    pub const fn variant(&self) -> Busstateselect {
46        match self.bits {
47            0 => Busstateselect::Unknown,
48            1 => Busstateselect::Idle,
49            2 => Busstateselect::Owner,
50            3 => Busstateselect::Busy,
51            _ => unreachable!(),
52        }
53    }
54    #[doc = "The Bus state is unknown to the I2C Host"]
55    #[inline(always)]
56    pub fn is_unknown(&self) -> bool {
57        *self == Busstateselect::Unknown
58    }
59    #[doc = "The Bus state is waiting for a transaction to be initialized"]
60    #[inline(always)]
61    pub fn is_idle(&self) -> bool {
62        *self == Busstateselect::Idle
63    }
64    #[doc = "The I2C Host is the current owner of the bus"]
65    #[inline(always)]
66    pub fn is_owner(&self) -> bool {
67        *self == Busstateselect::Owner
68    }
69    #[doc = "Some other I2C Host owns the bus"]
70    #[inline(always)]
71    pub fn is_busy(&self) -> bool {
72        *self == Busstateselect::Busy
73    }
74}
75#[doc = "Field `BUSSTATE` writer - Bus State"]
76pub type BusstateW<'a, REG> = crate::FieldWriter<'a, REG, 2, Busstateselect, crate::Safe>;
77impl<'a, REG> BusstateW<'a, REG>
78where
79    REG: crate::Writable + crate::RegisterSpec,
80    REG::Ux: From<u8>,
81{
82    #[doc = "The Bus state is unknown to the I2C Host"]
83    #[inline(always)]
84    pub fn unknown(self) -> &'a mut crate::W<REG> {
85        self.variant(Busstateselect::Unknown)
86    }
87    #[doc = "The Bus state is waiting for a transaction to be initialized"]
88    #[inline(always)]
89    pub fn idle(self) -> &'a mut crate::W<REG> {
90        self.variant(Busstateselect::Idle)
91    }
92    #[doc = "The I2C Host is the current owner of the bus"]
93    #[inline(always)]
94    pub fn owner(self) -> &'a mut crate::W<REG> {
95        self.variant(Busstateselect::Owner)
96    }
97    #[doc = "Some other I2C Host owns the bus"]
98    #[inline(always)]
99    pub fn busy(self) -> &'a mut crate::W<REG> {
100        self.variant(Busstateselect::Busy)
101    }
102}
103#[doc = "Field `LOWTOUT` reader - SCL Low Timeout"]
104pub type LowtoutR = crate::BitReader;
105#[doc = "Field `LOWTOUT` writer - SCL Low Timeout"]
106pub type LowtoutW<'a, REG> = crate::BitWriter<'a, REG>;
107#[doc = "Field `CLKHOLD` reader - Clock Hold"]
108pub type ClkholdR = crate::BitReader;
109#[doc = "Field `CLKHOLD` writer - Clock Hold"]
110pub type ClkholdW<'a, REG> = crate::BitWriter<'a, REG>;
111#[doc = "Field `MEXTTOUT` reader - Master SCL Low Extend Timeout"]
112pub type MexttoutR = crate::BitReader;
113#[doc = "Field `MEXTTOUT` writer - Master SCL Low Extend Timeout"]
114pub type MexttoutW<'a, REG> = crate::BitWriter<'a, REG>;
115#[doc = "Field `SEXTTOUT` reader - Slave SCL Low Extend Timeout"]
116pub type SexttoutR = crate::BitReader;
117#[doc = "Field `SEXTTOUT` writer - Slave SCL Low Extend Timeout"]
118pub type SexttoutW<'a, REG> = crate::BitWriter<'a, REG>;
119#[doc = "Field `LENERR` reader - Length Error"]
120pub type LenerrR = crate::BitReader;
121#[doc = "Field `LENERR` writer - Length Error"]
122pub type LenerrW<'a, REG> = crate::BitWriter<'a, REG>;
123impl R {
124    #[doc = "Bit 0 - Bus Error"]
125    #[inline(always)]
126    pub fn buserr(&self) -> BuserrR {
127        BuserrR::new((self.bits & 1) != 0)
128    }
129    #[doc = "Bit 1 - Arbitration Lost"]
130    #[inline(always)]
131    pub fn arblost(&self) -> ArblostR {
132        ArblostR::new(((self.bits >> 1) & 1) != 0)
133    }
134    #[doc = "Bit 2 - Received Not Acknowledge"]
135    #[inline(always)]
136    pub fn rxnack(&self) -> RxnackR {
137        RxnackR::new(((self.bits >> 2) & 1) != 0)
138    }
139    #[doc = "Bits 4:5 - Bus State"]
140    #[inline(always)]
141    pub fn busstate(&self) -> BusstateR {
142        BusstateR::new(((self.bits >> 4) & 3) as u8)
143    }
144    #[doc = "Bit 6 - SCL Low Timeout"]
145    #[inline(always)]
146    pub fn lowtout(&self) -> LowtoutR {
147        LowtoutR::new(((self.bits >> 6) & 1) != 0)
148    }
149    #[doc = "Bit 7 - Clock Hold"]
150    #[inline(always)]
151    pub fn clkhold(&self) -> ClkholdR {
152        ClkholdR::new(((self.bits >> 7) & 1) != 0)
153    }
154    #[doc = "Bit 8 - Master SCL Low Extend Timeout"]
155    #[inline(always)]
156    pub fn mexttout(&self) -> MexttoutR {
157        MexttoutR::new(((self.bits >> 8) & 1) != 0)
158    }
159    #[doc = "Bit 9 - Slave SCL Low Extend Timeout"]
160    #[inline(always)]
161    pub fn sexttout(&self) -> SexttoutR {
162        SexttoutR::new(((self.bits >> 9) & 1) != 0)
163    }
164    #[doc = "Bit 10 - Length Error"]
165    #[inline(always)]
166    pub fn lenerr(&self) -> LenerrR {
167        LenerrR::new(((self.bits >> 10) & 1) != 0)
168    }
169}
170impl W {
171    #[doc = "Bit 0 - Bus Error"]
172    #[inline(always)]
173    #[must_use]
174    pub fn buserr(&mut self) -> BuserrW<StatusSpec> {
175        BuserrW::new(self, 0)
176    }
177    #[doc = "Bit 1 - Arbitration Lost"]
178    #[inline(always)]
179    #[must_use]
180    pub fn arblost(&mut self) -> ArblostW<StatusSpec> {
181        ArblostW::new(self, 1)
182    }
183    #[doc = "Bit 2 - Received Not Acknowledge"]
184    #[inline(always)]
185    #[must_use]
186    pub fn rxnack(&mut self) -> RxnackW<StatusSpec> {
187        RxnackW::new(self, 2)
188    }
189    #[doc = "Bits 4:5 - Bus State"]
190    #[inline(always)]
191    #[must_use]
192    pub fn busstate(&mut self) -> BusstateW<StatusSpec> {
193        BusstateW::new(self, 4)
194    }
195    #[doc = "Bit 6 - SCL Low Timeout"]
196    #[inline(always)]
197    #[must_use]
198    pub fn lowtout(&mut self) -> LowtoutW<StatusSpec> {
199        LowtoutW::new(self, 6)
200    }
201    #[doc = "Bit 7 - Clock Hold"]
202    #[inline(always)]
203    #[must_use]
204    pub fn clkhold(&mut self) -> ClkholdW<StatusSpec> {
205        ClkholdW::new(self, 7)
206    }
207    #[doc = "Bit 8 - Master SCL Low Extend Timeout"]
208    #[inline(always)]
209    #[must_use]
210    pub fn mexttout(&mut self) -> MexttoutW<StatusSpec> {
211        MexttoutW::new(self, 8)
212    }
213    #[doc = "Bit 9 - Slave SCL Low Extend Timeout"]
214    #[inline(always)]
215    #[must_use]
216    pub fn sexttout(&mut self) -> SexttoutW<StatusSpec> {
217        SexttoutW::new(self, 9)
218    }
219    #[doc = "Bit 10 - Length Error"]
220    #[inline(always)]
221    #[must_use]
222    pub fn lenerr(&mut self) -> LenerrW<StatusSpec> {
223        LenerrW::new(self, 10)
224    }
225}
226#[doc = "I2CM Status\n\nYou can [`read`](crate::Reg::read) this register and get [`status::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`status::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
227pub struct StatusSpec;
228impl crate::RegisterSpec for StatusSpec {
229    type Ux = u16;
230}
231#[doc = "`read()` method returns [`status::R`](R) reader structure"]
232impl crate::Readable for StatusSpec {}
233#[doc = "`write(|w| ..)` method takes [`status::W`](W) writer structure"]
234impl crate::Writable for StatusSpec {
235    type Safety = crate::Unsafe;
236    const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0;
237    const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0;
238}
239#[doc = "`reset()` method sets STATUS to value 0"]
240impl crate::Resettable for StatusSpec {
241    const RESET_VALUE: u16 = 0;
242}
atsamd51j/sercom0/i2cm/status.rs

atsamd51j/sercom0/i2cm/
status.rs
