atsamd51j/
gclk.rs

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1#[repr(C)]
2#[doc = "Register block"]
3pub struct RegisterBlock {
4    ctrla: Ctrla,
5    _reserved1: [u8; 0x03],
6    syncbusy: Syncbusy,
7    _reserved2: [u8; 0x18],
8    genctrl: [Genctrl; 12],
9    _reserved3: [u8; 0x30],
10    pchctrl: [Pchctrl; 48],
11}
12impl RegisterBlock {
13    #[doc = "0x00 - Control"]
14    #[inline(always)]
15    pub const fn ctrla(&self) -> &Ctrla {
16        &self.ctrla
17    }
18    #[doc = "0x04 - Synchronization Busy"]
19    #[inline(always)]
20    pub const fn syncbusy(&self) -> &Syncbusy {
21        &self.syncbusy
22    }
23    #[doc = "0x20..0x50 - Generic Clock Generator Control"]
24    #[inline(always)]
25    pub const fn genctrl(&self, n: usize) -> &Genctrl {
26        &self.genctrl[n]
27    }
28    #[doc = "Iterator for array of:"]
29    #[doc = "0x20..0x50 - Generic Clock Generator Control"]
30    #[inline(always)]
31    pub fn genctrl_iter(&self) -> impl Iterator<Item = &Genctrl> {
32        self.genctrl.iter()
33    }
34    #[doc = "0x80..0x140 - Peripheral Clock Control"]
35    #[inline(always)]
36    pub const fn pchctrl(&self, n: usize) -> &Pchctrl {
37        &self.pchctrl[n]
38    }
39    #[doc = "Iterator for array of:"]
40    #[doc = "0x80..0x140 - Peripheral Clock Control"]
41    #[inline(always)]
42    pub fn pchctrl_iter(&self) -> impl Iterator<Item = &Pchctrl> {
43        self.pchctrl.iter()
44    }
45}
46#[doc = "CTRLA (rw) register accessor: Control\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrla::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrla::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrla`]
47module"]
48#[doc(alias = "CTRLA")]
49pub type Ctrla = crate::Reg<ctrla::CtrlaSpec>;
50#[doc = "Control"]
51pub mod ctrla;
52#[doc = "SYNCBUSY (r) register accessor: Synchronization Busy\n\nYou can [`read`](crate::Reg::read) this register and get [`syncbusy::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@syncbusy`]
53module"]
54#[doc(alias = "SYNCBUSY")]
55pub type Syncbusy = crate::Reg<syncbusy::SyncbusySpec>;
56#[doc = "Synchronization Busy"]
57pub mod syncbusy;
58#[doc = "GENCTRL (rw) register accessor: Generic Clock Generator Control\n\nYou can [`read`](crate::Reg::read) this register and get [`genctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`genctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@genctrl`]
59module"]
60#[doc(alias = "GENCTRL")]
61pub type Genctrl = crate::Reg<genctrl::GenctrlSpec>;
62#[doc = "Generic Clock Generator Control"]
63pub mod genctrl;
64#[doc = "PCHCTRL (rw) register accessor: Peripheral Clock Control\n\nYou can [`read`](crate::Reg::read) this register and get [`pchctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pchctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pchctrl`]
65module"]
66#[doc(alias = "PCHCTRL")]
67pub type Pchctrl = crate::Reg<pchctrl::PchctrlSpec>;
68#[doc = "Peripheral Clock Control"]
69pub mod pchctrl;
atsamd51j/gclk.rs

atsamd51j/
gclk.rs
