atsamd51j/oscctrl/
dfllctrlb.rs

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1#[doc = "Register `DFLLCTRLB` reader"]
2pub type R = crate::R<DfllctrlbSpec>;
3#[doc = "Register `DFLLCTRLB` writer"]
4pub type W = crate::W<DfllctrlbSpec>;
5#[doc = "Field `MODE` reader - Operating Mode Selection"]
6pub type ModeR = crate::BitReader;
7#[doc = "Field `MODE` writer - Operating Mode Selection"]
8pub type ModeW<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `STABLE` reader - Stable DFLL Frequency"]
10pub type StableR = crate::BitReader;
11#[doc = "Field `STABLE` writer - Stable DFLL Frequency"]
12pub type StableW<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `LLAW` reader - Lose Lock After Wake"]
14pub type LlawR = crate::BitReader;
15#[doc = "Field `LLAW` writer - Lose Lock After Wake"]
16pub type LlawW<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `USBCRM` reader - USB Clock Recovery Mode"]
18pub type UsbcrmR = crate::BitReader;
19#[doc = "Field `USBCRM` writer - USB Clock Recovery Mode"]
20pub type UsbcrmW<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `CCDIS` reader - Chill Cycle Disable"]
22pub type CcdisR = crate::BitReader;
23#[doc = "Field `CCDIS` writer - Chill Cycle Disable"]
24pub type CcdisW<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `QLDIS` reader - Quick Lock Disable"]
26pub type QldisR = crate::BitReader;
27#[doc = "Field `QLDIS` writer - Quick Lock Disable"]
28pub type QldisW<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `BPLCKC` reader - Bypass Coarse Lock"]
30pub type BplckcR = crate::BitReader;
31#[doc = "Field `BPLCKC` writer - Bypass Coarse Lock"]
32pub type BplckcW<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `WAITLOCK` reader - Wait Lock"]
34pub type WaitlockR = crate::BitReader;
35#[doc = "Field `WAITLOCK` writer - Wait Lock"]
36pub type WaitlockW<'a, REG> = crate::BitWriter<'a, REG>;
37impl R {
38    #[doc = "Bit 0 - Operating Mode Selection"]
39    #[inline(always)]
40    pub fn mode(&self) -> ModeR {
41        ModeR::new((self.bits & 1) != 0)
42    }
43    #[doc = "Bit 1 - Stable DFLL Frequency"]
44    #[inline(always)]
45    pub fn stable(&self) -> StableR {
46        StableR::new(((self.bits >> 1) & 1) != 0)
47    }
48    #[doc = "Bit 2 - Lose Lock After Wake"]
49    #[inline(always)]
50    pub fn llaw(&self) -> LlawR {
51        LlawR::new(((self.bits >> 2) & 1) != 0)
52    }
53    #[doc = "Bit 3 - USB Clock Recovery Mode"]
54    #[inline(always)]
55    pub fn usbcrm(&self) -> UsbcrmR {
56        UsbcrmR::new(((self.bits >> 3) & 1) != 0)
57    }
58    #[doc = "Bit 4 - Chill Cycle Disable"]
59    #[inline(always)]
60    pub fn ccdis(&self) -> CcdisR {
61        CcdisR::new(((self.bits >> 4) & 1) != 0)
62    }
63    #[doc = "Bit 5 - Quick Lock Disable"]
64    #[inline(always)]
65    pub fn qldis(&self) -> QldisR {
66        QldisR::new(((self.bits >> 5) & 1) != 0)
67    }
68    #[doc = "Bit 6 - Bypass Coarse Lock"]
69    #[inline(always)]
70    pub fn bplckc(&self) -> BplckcR {
71        BplckcR::new(((self.bits >> 6) & 1) != 0)
72    }
73    #[doc = "Bit 7 - Wait Lock"]
74    #[inline(always)]
75    pub fn waitlock(&self) -> WaitlockR {
76        WaitlockR::new(((self.bits >> 7) & 1) != 0)
77    }
78}
79impl W {
80    #[doc = "Bit 0 - Operating Mode Selection"]
81    #[inline(always)]
82    #[must_use]
83    pub fn mode(&mut self) -> ModeW<DfllctrlbSpec> {
84        ModeW::new(self, 0)
85    }
86    #[doc = "Bit 1 - Stable DFLL Frequency"]
87    #[inline(always)]
88    #[must_use]
89    pub fn stable(&mut self) -> StableW<DfllctrlbSpec> {
90        StableW::new(self, 1)
91    }
92    #[doc = "Bit 2 - Lose Lock After Wake"]
93    #[inline(always)]
94    #[must_use]
95    pub fn llaw(&mut self) -> LlawW<DfllctrlbSpec> {
96        LlawW::new(self, 2)
97    }
98    #[doc = "Bit 3 - USB Clock Recovery Mode"]
99    #[inline(always)]
100    #[must_use]
101    pub fn usbcrm(&mut self) -> UsbcrmW<DfllctrlbSpec> {
102        UsbcrmW::new(self, 3)
103    }
104    #[doc = "Bit 4 - Chill Cycle Disable"]
105    #[inline(always)]
106    #[must_use]
107    pub fn ccdis(&mut self) -> CcdisW<DfllctrlbSpec> {
108        CcdisW::new(self, 4)
109    }
110    #[doc = "Bit 5 - Quick Lock Disable"]
111    #[inline(always)]
112    #[must_use]
113    pub fn qldis(&mut self) -> QldisW<DfllctrlbSpec> {
114        QldisW::new(self, 5)
115    }
116    #[doc = "Bit 6 - Bypass Coarse Lock"]
117    #[inline(always)]
118    #[must_use]
119    pub fn bplckc(&mut self) -> BplckcW<DfllctrlbSpec> {
120        BplckcW::new(self, 6)
121    }
122    #[doc = "Bit 7 - Wait Lock"]
123    #[inline(always)]
124    #[must_use]
125    pub fn waitlock(&mut self) -> WaitlockW<DfllctrlbSpec> {
126        WaitlockW::new(self, 7)
127    }
128}
129#[doc = "DFLL48M Control B\n\nYou can [`read`](crate::Reg::read) this register and get [`dfllctrlb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfllctrlb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
130pub struct DfllctrlbSpec;
131impl crate::RegisterSpec for DfllctrlbSpec {
132    type Ux = u8;
133}
134#[doc = "`read()` method returns [`dfllctrlb::R`](R) reader structure"]
135impl crate::Readable for DfllctrlbSpec {}
136#[doc = "`write(|w| ..)` method takes [`dfllctrlb::W`](W) writer structure"]
137impl crate::Writable for DfllctrlbSpec {
138    type Safety = crate::Unsafe;
139    const ZERO_TO_MODIFY_FIELDS_BITMAP: u8 = 0;
140    const ONE_TO_MODIFY_FIELDS_BITMAP: u8 = 0;
141}
142#[doc = "`reset()` method sets DFLLCTRLB to value 0"]
143impl crate::Resettable for DfllctrlbSpec {
144    const RESET_VALUE: u8 = 0;
145}
atsamd51j/oscctrl/dfllctrlb.rs

atsamd51j/oscctrl/
dfllctrlb.rs
