atsamd51j/port/group/
evctrl.rs

Help
1#[doc = "Register `EVCTRL` reader"]
2pub type R = crate::R<EvctrlSpec>;
3#[doc = "Register `EVCTRL` writer"]
4pub type W = crate::W<EvctrlSpec>;
5#[doc = "Field `PID0` reader - PORT Event Pin Identifier 0"]
6pub type Pid0R = crate::FieldReader;
7#[doc = "Field `PID0` writer - PORT Event Pin Identifier 0"]
8pub type Pid0W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
9#[doc = "PORT Event Action 0\n\nValue on reset: 0"]
10#[derive(Clone, Copy, Debug, PartialEq, Eq)]
11#[repr(u8)]
12pub enum Evact0select {
13    #[doc = "0: Event output to pin"]
14    Out = 0,
15    #[doc = "1: Set output register of pin on event"]
16    Set = 1,
17    #[doc = "2: Clear output register of pin on event"]
18    Clr = 2,
19    #[doc = "3: Toggle output register of pin on event"]
20    Tgl = 3,
21}
22impl From<Evact0select> for u8 {
23    #[inline(always)]
24    fn from(variant: Evact0select) -> Self {
25        variant as _
26    }
27}
28impl crate::FieldSpec for Evact0select {
29    type Ux = u8;
30}
31impl crate::IsEnum for Evact0select {}
32#[doc = "Field `EVACT0` reader - PORT Event Action 0"]
33pub type Evact0R = crate::FieldReader<Evact0select>;
34impl Evact0R {
35    #[doc = "Get enumerated values variant"]
36    #[inline(always)]
37    pub const fn variant(&self) -> Evact0select {
38        match self.bits {
39            0 => Evact0select::Out,
40            1 => Evact0select::Set,
41            2 => Evact0select::Clr,
42            3 => Evact0select::Tgl,
43            _ => unreachable!(),
44        }
45    }
46    #[doc = "Event output to pin"]
47    #[inline(always)]
48    pub fn is_out(&self) -> bool {
49        *self == Evact0select::Out
50    }
51    #[doc = "Set output register of pin on event"]
52    #[inline(always)]
53    pub fn is_set(&self) -> bool {
54        *self == Evact0select::Set
55    }
56    #[doc = "Clear output register of pin on event"]
57    #[inline(always)]
58    pub fn is_clr(&self) -> bool {
59        *self == Evact0select::Clr
60    }
61    #[doc = "Toggle output register of pin on event"]
62    #[inline(always)]
63    pub fn is_tgl(&self) -> bool {
64        *self == Evact0select::Tgl
65    }
66}
67#[doc = "Field `EVACT0` writer - PORT Event Action 0"]
68pub type Evact0W<'a, REG> = crate::FieldWriter<'a, REG, 2, Evact0select, crate::Safe>;
69impl<'a, REG> Evact0W<'a, REG>
70where
71    REG: crate::Writable + crate::RegisterSpec,
72    REG::Ux: From<u8>,
73{
74    #[doc = "Event output to pin"]
75    #[inline(always)]
76    pub fn out(self) -> &'a mut crate::W<REG> {
77        self.variant(Evact0select::Out)
78    }
79    #[doc = "Set output register of pin on event"]
80    #[inline(always)]
81    pub fn set_(self) -> &'a mut crate::W<REG> {
82        self.variant(Evact0select::Set)
83    }
84    #[doc = "Clear output register of pin on event"]
85    #[inline(always)]
86    pub fn clr(self) -> &'a mut crate::W<REG> {
87        self.variant(Evact0select::Clr)
88    }
89    #[doc = "Toggle output register of pin on event"]
90    #[inline(always)]
91    pub fn tgl(self) -> &'a mut crate::W<REG> {
92        self.variant(Evact0select::Tgl)
93    }
94}
95#[doc = "Field `PORTEI0` reader - PORT Event Input Enable 0"]
96pub type Portei0R = crate::BitReader;
97#[doc = "Field `PORTEI0` writer - PORT Event Input Enable 0"]
98pub type Portei0W<'a, REG> = crate::BitWriter<'a, REG>;
99#[doc = "Field `PID1` reader - PORT Event Pin Identifier 1"]
100pub type Pid1R = crate::FieldReader;
101#[doc = "Field `PID1` writer - PORT Event Pin Identifier 1"]
102pub type Pid1W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
103#[doc = "Field `EVACT1` reader - PORT Event Action 1"]
104pub type Evact1R = crate::FieldReader;
105#[doc = "Field `EVACT1` writer - PORT Event Action 1"]
106pub type Evact1W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
107#[doc = "Field `PORTEI1` reader - PORT Event Input Enable 1"]
108pub type Portei1R = crate::BitReader;
109#[doc = "Field `PORTEI1` writer - PORT Event Input Enable 1"]
110pub type Portei1W<'a, REG> = crate::BitWriter<'a, REG>;
111#[doc = "Field `PID2` reader - PORT Event Pin Identifier 2"]
112pub type Pid2R = crate::FieldReader;
113#[doc = "Field `PID2` writer - PORT Event Pin Identifier 2"]
114pub type Pid2W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
115#[doc = "Field `EVACT2` reader - PORT Event Action 2"]
116pub type Evact2R = crate::FieldReader;
117#[doc = "Field `EVACT2` writer - PORT Event Action 2"]
118pub type Evact2W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
119#[doc = "Field `PORTEI2` reader - PORT Event Input Enable 2"]
120pub type Portei2R = crate::BitReader;
121#[doc = "Field `PORTEI2` writer - PORT Event Input Enable 2"]
122pub type Portei2W<'a, REG> = crate::BitWriter<'a, REG>;
123#[doc = "Field `PID3` reader - PORT Event Pin Identifier 3"]
124pub type Pid3R = crate::FieldReader;
125#[doc = "Field `PID3` writer - PORT Event Pin Identifier 3"]
126pub type Pid3W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
127#[doc = "Field `EVACT3` reader - PORT Event Action 3"]
128pub type Evact3R = crate::FieldReader;
129#[doc = "Field `EVACT3` writer - PORT Event Action 3"]
130pub type Evact3W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
131#[doc = "Field `PORTEI3` reader - PORT Event Input Enable 3"]
132pub type Portei3R = crate::BitReader;
133#[doc = "Field `PORTEI3` writer - PORT Event Input Enable 3"]
134pub type Portei3W<'a, REG> = crate::BitWriter<'a, REG>;
135impl R {
136    #[doc = "Bits 0:4 - PORT Event Pin Identifier 0"]
137    #[inline(always)]
138    pub fn pid0(&self) -> Pid0R {
139        Pid0R::new((self.bits & 0x1f) as u8)
140    }
141    #[doc = "Bits 5:6 - PORT Event Action 0"]
142    #[inline(always)]
143    pub fn evact0(&self) -> Evact0R {
144        Evact0R::new(((self.bits >> 5) & 3) as u8)
145    }
146    #[doc = "Bit 7 - PORT Event Input Enable 0"]
147    #[inline(always)]
148    pub fn portei0(&self) -> Portei0R {
149        Portei0R::new(((self.bits >> 7) & 1) != 0)
150    }
151    #[doc = "Bits 8:12 - PORT Event Pin Identifier 1"]
152    #[inline(always)]
153    pub fn pid1(&self) -> Pid1R {
154        Pid1R::new(((self.bits >> 8) & 0x1f) as u8)
155    }
156    #[doc = "Bits 13:14 - PORT Event Action 1"]
157    #[inline(always)]
158    pub fn evact1(&self) -> Evact1R {
159        Evact1R::new(((self.bits >> 13) & 3) as u8)
160    }
161    #[doc = "Bit 15 - PORT Event Input Enable 1"]
162    #[inline(always)]
163    pub fn portei1(&self) -> Portei1R {
164        Portei1R::new(((self.bits >> 15) & 1) != 0)
165    }
166    #[doc = "Bits 16:20 - PORT Event Pin Identifier 2"]
167    #[inline(always)]
168    pub fn pid2(&self) -> Pid2R {
169        Pid2R::new(((self.bits >> 16) & 0x1f) as u8)
170    }
171    #[doc = "Bits 21:22 - PORT Event Action 2"]
172    #[inline(always)]
173    pub fn evact2(&self) -> Evact2R {
174        Evact2R::new(((self.bits >> 21) & 3) as u8)
175    }
176    #[doc = "Bit 23 - PORT Event Input Enable 2"]
177    #[inline(always)]
178    pub fn portei2(&self) -> Portei2R {
179        Portei2R::new(((self.bits >> 23) & 1) != 0)
180    }
181    #[doc = "Bits 24:28 - PORT Event Pin Identifier 3"]
182    #[inline(always)]
183    pub fn pid3(&self) -> Pid3R {
184        Pid3R::new(((self.bits >> 24) & 0x1f) as u8)
185    }
186    #[doc = "Bits 29:30 - PORT Event Action 3"]
187    #[inline(always)]
188    pub fn evact3(&self) -> Evact3R {
189        Evact3R::new(((self.bits >> 29) & 3) as u8)
190    }
191    #[doc = "Bit 31 - PORT Event Input Enable 3"]
192    #[inline(always)]
193    pub fn portei3(&self) -> Portei3R {
194        Portei3R::new(((self.bits >> 31) & 1) != 0)
195    }
196}
197impl W {
198    #[doc = "Bits 0:4 - PORT Event Pin Identifier 0"]
199    #[inline(always)]
200    #[must_use]
201    pub fn pid0(&mut self) -> Pid0W<EvctrlSpec> {
202        Pid0W::new(self, 0)
203    }
204    #[doc = "Bits 5:6 - PORT Event Action 0"]
205    #[inline(always)]
206    #[must_use]
207    pub fn evact0(&mut self) -> Evact0W<EvctrlSpec> {
208        Evact0W::new(self, 5)
209    }
210    #[doc = "Bit 7 - PORT Event Input Enable 0"]
211    #[inline(always)]
212    #[must_use]
213    pub fn portei0(&mut self) -> Portei0W<EvctrlSpec> {
214        Portei0W::new(self, 7)
215    }
216    #[doc = "Bits 8:12 - PORT Event Pin Identifier 1"]
217    #[inline(always)]
218    #[must_use]
219    pub fn pid1(&mut self) -> Pid1W<EvctrlSpec> {
220        Pid1W::new(self, 8)
221    }
222    #[doc = "Bits 13:14 - PORT Event Action 1"]
223    #[inline(always)]
224    #[must_use]
225    pub fn evact1(&mut self) -> Evact1W<EvctrlSpec> {
226        Evact1W::new(self, 13)
227    }
228    #[doc = "Bit 15 - PORT Event Input Enable 1"]
229    #[inline(always)]
230    #[must_use]
231    pub fn portei1(&mut self) -> Portei1W<EvctrlSpec> {
232        Portei1W::new(self, 15)
233    }
234    #[doc = "Bits 16:20 - PORT Event Pin Identifier 2"]
235    #[inline(always)]
236    #[must_use]
237    pub fn pid2(&mut self) -> Pid2W<EvctrlSpec> {
238        Pid2W::new(self, 16)
239    }
240    #[doc = "Bits 21:22 - PORT Event Action 2"]
241    #[inline(always)]
242    #[must_use]
243    pub fn evact2(&mut self) -> Evact2W<EvctrlSpec> {
244        Evact2W::new(self, 21)
245    }
246    #[doc = "Bit 23 - PORT Event Input Enable 2"]
247    #[inline(always)]
248    #[must_use]
249    pub fn portei2(&mut self) -> Portei2W<EvctrlSpec> {
250        Portei2W::new(self, 23)
251    }
252    #[doc = "Bits 24:28 - PORT Event Pin Identifier 3"]
253    #[inline(always)]
254    #[must_use]
255    pub fn pid3(&mut self) -> Pid3W<EvctrlSpec> {
256        Pid3W::new(self, 24)
257    }
258    #[doc = "Bits 29:30 - PORT Event Action 3"]
259    #[inline(always)]
260    #[must_use]
261    pub fn evact3(&mut self) -> Evact3W<EvctrlSpec> {
262        Evact3W::new(self, 29)
263    }
264    #[doc = "Bit 31 - PORT Event Input Enable 3"]
265    #[inline(always)]
266    #[must_use]
267    pub fn portei3(&mut self) -> Portei3W<EvctrlSpec> {
268        Portei3W::new(self, 31)
269    }
270}
271#[doc = "Event Input Control\n\nYou can [`read`](crate::Reg::read) this register and get [`evctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`evctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
272pub struct EvctrlSpec;
273impl crate::RegisterSpec for EvctrlSpec {
274    type Ux = u32;
275}
276#[doc = "`read()` method returns [`evctrl::R`](R) reader structure"]
277impl crate::Readable for EvctrlSpec {}
278#[doc = "`write(|w| ..)` method takes [`evctrl::W`](W) writer structure"]
279impl crate::Writable for EvctrlSpec {
280    type Safety = crate::Unsafe;
281    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
282    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
283}
284#[doc = "`reset()` method sets EVCTRL to value 0"]
285impl crate::Resettable for EvctrlSpec {
286    const RESET_VALUE: u32 = 0;
287}
atsamd51j/port/group/evctrl.rs

atsamd51j/port/group/
evctrl.rs
