atsamd51j/rtc/mode0/
ctrla.rs

Help
1#[doc = "Register `CTRLA` reader"]
2pub type R = crate::R<CtrlaSpec>;
3#[doc = "Register `CTRLA` writer"]
4pub type W = crate::W<CtrlaSpec>;
5#[doc = "Field `SWRST` reader - Software Reset"]
6pub type SwrstR = crate::BitReader;
7#[doc = "Field `SWRST` writer - Software Reset"]
8pub type SwrstW<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `ENABLE` reader - Enable"]
10pub type EnableR = crate::BitReader;
11#[doc = "Field `ENABLE` writer - Enable"]
12pub type EnableW<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Operating Mode\n\nValue on reset: 0"]
14#[derive(Clone, Copy, Debug, PartialEq, Eq)]
15#[repr(u8)]
16pub enum Modeselect {
17    #[doc = "0: Mode 0: 32-bit Counter"]
18    Count32 = 0,
19    #[doc = "1: Mode 1: 16-bit Counter"]
20    Count16 = 1,
21    #[doc = "2: Mode 2: Clock/Calendar"]
22    Clock = 2,
23}
24impl From<Modeselect> for u8 {
25    #[inline(always)]
26    fn from(variant: Modeselect) -> Self {
27        variant as _
28    }
29}
30impl crate::FieldSpec for Modeselect {
31    type Ux = u8;
32}
33impl crate::IsEnum for Modeselect {}
34#[doc = "Field `MODE` reader - Operating Mode"]
35pub type ModeR = crate::FieldReader<Modeselect>;
36impl ModeR {
37    #[doc = "Get enumerated values variant"]
38    #[inline(always)]
39    pub const fn variant(&self) -> Option<Modeselect> {
40        match self.bits {
41            0 => Some(Modeselect::Count32),
42            1 => Some(Modeselect::Count16),
43            2 => Some(Modeselect::Clock),
44            _ => None,
45        }
46    }
47    #[doc = "Mode 0: 32-bit Counter"]
48    #[inline(always)]
49    pub fn is_count32(&self) -> bool {
50        *self == Modeselect::Count32
51    }
52    #[doc = "Mode 1: 16-bit Counter"]
53    #[inline(always)]
54    pub fn is_count16(&self) -> bool {
55        *self == Modeselect::Count16
56    }
57    #[doc = "Mode 2: Clock/Calendar"]
58    #[inline(always)]
59    pub fn is_clock(&self) -> bool {
60        *self == Modeselect::Clock
61    }
62}
63#[doc = "Field `MODE` writer - Operating Mode"]
64pub type ModeW<'a, REG> = crate::FieldWriter<'a, REG, 2, Modeselect>;
65impl<'a, REG> ModeW<'a, REG>
66where
67    REG: crate::Writable + crate::RegisterSpec,
68    REG::Ux: From<u8>,
69{
70    #[doc = "Mode 0: 32-bit Counter"]
71    #[inline(always)]
72    pub fn count32(self) -> &'a mut crate::W<REG> {
73        self.variant(Modeselect::Count32)
74    }
75    #[doc = "Mode 1: 16-bit Counter"]
76    #[inline(always)]
77    pub fn count16(self) -> &'a mut crate::W<REG> {
78        self.variant(Modeselect::Count16)
79    }
80    #[doc = "Mode 2: Clock/Calendar"]
81    #[inline(always)]
82    pub fn clock(self) -> &'a mut crate::W<REG> {
83        self.variant(Modeselect::Clock)
84    }
85}
86#[doc = "Field `MATCHCLR` reader - Clear on Match"]
87pub type MatchclrR = crate::BitReader;
88#[doc = "Field `MATCHCLR` writer - Clear on Match"]
89pub type MatchclrW<'a, REG> = crate::BitWriter<'a, REG>;
90#[doc = "Prescaler\n\nValue on reset: 0"]
91#[derive(Clone, Copy, Debug, PartialEq, Eq)]
92#[repr(u8)]
93pub enum Prescalerselect {
94    #[doc = "0: CLK_RTC_CNT = GCLK_RTC/1"]
95    Off = 0,
96    #[doc = "1: CLK_RTC_CNT = GCLK_RTC/1"]
97    Div1 = 1,
98    #[doc = "2: CLK_RTC_CNT = GCLK_RTC/2"]
99    Div2 = 2,
100    #[doc = "3: CLK_RTC_CNT = GCLK_RTC/4"]
101    Div4 = 3,
102    #[doc = "4: CLK_RTC_CNT = GCLK_RTC/8"]
103    Div8 = 4,
104    #[doc = "5: CLK_RTC_CNT = GCLK_RTC/16"]
105    Div16 = 5,
106    #[doc = "6: CLK_RTC_CNT = GCLK_RTC/32"]
107    Div32 = 6,
108    #[doc = "7: CLK_RTC_CNT = GCLK_RTC/64"]
109    Div64 = 7,
110    #[doc = "8: CLK_RTC_CNT = GCLK_RTC/128"]
111    Div128 = 8,
112    #[doc = "9: CLK_RTC_CNT = GCLK_RTC/256"]
113    Div256 = 9,
114    #[doc = "10: CLK_RTC_CNT = GCLK_RTC/512"]
115    Div512 = 10,
116    #[doc = "11: CLK_RTC_CNT = GCLK_RTC/1024"]
117    Div1024 = 11,
118}
119impl From<Prescalerselect> for u8 {
120    #[inline(always)]
121    fn from(variant: Prescalerselect) -> Self {
122        variant as _
123    }
124}
125impl crate::FieldSpec for Prescalerselect {
126    type Ux = u8;
127}
128impl crate::IsEnum for Prescalerselect {}
129#[doc = "Field `PRESCALER` reader - Prescaler"]
130pub type PrescalerR = crate::FieldReader<Prescalerselect>;
131impl PrescalerR {
132    #[doc = "Get enumerated values variant"]
133    #[inline(always)]
134    pub const fn variant(&self) -> Option<Prescalerselect> {
135        match self.bits {
136            0 => Some(Prescalerselect::Off),
137            1 => Some(Prescalerselect::Div1),
138            2 => Some(Prescalerselect::Div2),
139            3 => Some(Prescalerselect::Div4),
140            4 => Some(Prescalerselect::Div8),
141            5 => Some(Prescalerselect::Div16),
142            6 => Some(Prescalerselect::Div32),
143            7 => Some(Prescalerselect::Div64),
144            8 => Some(Prescalerselect::Div128),
145            9 => Some(Prescalerselect::Div256),
146            10 => Some(Prescalerselect::Div512),
147            11 => Some(Prescalerselect::Div1024),
148            _ => None,
149        }
150    }
151    #[doc = "CLK_RTC_CNT = GCLK_RTC/1"]
152    #[inline(always)]
153    pub fn is_off(&self) -> bool {
154        *self == Prescalerselect::Off
155    }
156    #[doc = "CLK_RTC_CNT = GCLK_RTC/1"]
157    #[inline(always)]
158    pub fn is_div1(&self) -> bool {
159        *self == Prescalerselect::Div1
160    }
161    #[doc = "CLK_RTC_CNT = GCLK_RTC/2"]
162    #[inline(always)]
163    pub fn is_div2(&self) -> bool {
164        *self == Prescalerselect::Div2
165    }
166    #[doc = "CLK_RTC_CNT = GCLK_RTC/4"]
167    #[inline(always)]
168    pub fn is_div4(&self) -> bool {
169        *self == Prescalerselect::Div4
170    }
171    #[doc = "CLK_RTC_CNT = GCLK_RTC/8"]
172    #[inline(always)]
173    pub fn is_div8(&self) -> bool {
174        *self == Prescalerselect::Div8
175    }
176    #[doc = "CLK_RTC_CNT = GCLK_RTC/16"]
177    #[inline(always)]
178    pub fn is_div16(&self) -> bool {
179        *self == Prescalerselect::Div16
180    }
181    #[doc = "CLK_RTC_CNT = GCLK_RTC/32"]
182    #[inline(always)]
183    pub fn is_div32(&self) -> bool {
184        *self == Prescalerselect::Div32
185    }
186    #[doc = "CLK_RTC_CNT = GCLK_RTC/64"]
187    #[inline(always)]
188    pub fn is_div64(&self) -> bool {
189        *self == Prescalerselect::Div64
190    }
191    #[doc = "CLK_RTC_CNT = GCLK_RTC/128"]
192    #[inline(always)]
193    pub fn is_div128(&self) -> bool {
194        *self == Prescalerselect::Div128
195    }
196    #[doc = "CLK_RTC_CNT = GCLK_RTC/256"]
197    #[inline(always)]
198    pub fn is_div256(&self) -> bool {
199        *self == Prescalerselect::Div256
200    }
201    #[doc = "CLK_RTC_CNT = GCLK_RTC/512"]
202    #[inline(always)]
203    pub fn is_div512(&self) -> bool {
204        *self == Prescalerselect::Div512
205    }
206    #[doc = "CLK_RTC_CNT = GCLK_RTC/1024"]
207    #[inline(always)]
208    pub fn is_div1024(&self) -> bool {
209        *self == Prescalerselect::Div1024
210    }
211}
212#[doc = "Field `PRESCALER` writer - Prescaler"]
213pub type PrescalerW<'a, REG> = crate::FieldWriter<'a, REG, 4, Prescalerselect>;
214impl<'a, REG> PrescalerW<'a, REG>
215where
216    REG: crate::Writable + crate::RegisterSpec,
217    REG::Ux: From<u8>,
218{
219    #[doc = "CLK_RTC_CNT = GCLK_RTC/1"]
220    #[inline(always)]
221    pub fn off(self) -> &'a mut crate::W<REG> {
222        self.variant(Prescalerselect::Off)
223    }
224    #[doc = "CLK_RTC_CNT = GCLK_RTC/1"]
225    #[inline(always)]
226    pub fn div1(self) -> &'a mut crate::W<REG> {
227        self.variant(Prescalerselect::Div1)
228    }
229    #[doc = "CLK_RTC_CNT = GCLK_RTC/2"]
230    #[inline(always)]
231    pub fn div2(self) -> &'a mut crate::W<REG> {
232        self.variant(Prescalerselect::Div2)
233    }
234    #[doc = "CLK_RTC_CNT = GCLK_RTC/4"]
235    #[inline(always)]
236    pub fn div4(self) -> &'a mut crate::W<REG> {
237        self.variant(Prescalerselect::Div4)
238    }
239    #[doc = "CLK_RTC_CNT = GCLK_RTC/8"]
240    #[inline(always)]
241    pub fn div8(self) -> &'a mut crate::W<REG> {
242        self.variant(Prescalerselect::Div8)
243    }
244    #[doc = "CLK_RTC_CNT = GCLK_RTC/16"]
245    #[inline(always)]
246    pub fn div16(self) -> &'a mut crate::W<REG> {
247        self.variant(Prescalerselect::Div16)
248    }
249    #[doc = "CLK_RTC_CNT = GCLK_RTC/32"]
250    #[inline(always)]
251    pub fn div32(self) -> &'a mut crate::W<REG> {
252        self.variant(Prescalerselect::Div32)
253    }
254    #[doc = "CLK_RTC_CNT = GCLK_RTC/64"]
255    #[inline(always)]
256    pub fn div64(self) -> &'a mut crate::W<REG> {
257        self.variant(Prescalerselect::Div64)
258    }
259    #[doc = "CLK_RTC_CNT = GCLK_RTC/128"]
260    #[inline(always)]
261    pub fn div128(self) -> &'a mut crate::W<REG> {
262        self.variant(Prescalerselect::Div128)
263    }
264    #[doc = "CLK_RTC_CNT = GCLK_RTC/256"]
265    #[inline(always)]
266    pub fn div256(self) -> &'a mut crate::W<REG> {
267        self.variant(Prescalerselect::Div256)
268    }
269    #[doc = "CLK_RTC_CNT = GCLK_RTC/512"]
270    #[inline(always)]
271    pub fn div512(self) -> &'a mut crate::W<REG> {
272        self.variant(Prescalerselect::Div512)
273    }
274    #[doc = "CLK_RTC_CNT = GCLK_RTC/1024"]
275    #[inline(always)]
276    pub fn div1024(self) -> &'a mut crate::W<REG> {
277        self.variant(Prescalerselect::Div1024)
278    }
279}
280#[doc = "Field `BKTRST` reader - BKUP Registers Reset On Tamper Enable"]
281pub type BktrstR = crate::BitReader;
282#[doc = "Field `BKTRST` writer - BKUP Registers Reset On Tamper Enable"]
283pub type BktrstW<'a, REG> = crate::BitWriter<'a, REG>;
284#[doc = "Field `GPTRST` reader - GP Registers Reset On Tamper Enable"]
285pub type GptrstR = crate::BitReader;
286#[doc = "Field `GPTRST` writer - GP Registers Reset On Tamper Enable"]
287pub type GptrstW<'a, REG> = crate::BitWriter<'a, REG>;
288#[doc = "Field `COUNTSYNC` reader - Count Read Synchronization Enable"]
289pub type CountsyncR = crate::BitReader;
290#[doc = "Field `COUNTSYNC` writer - Count Read Synchronization Enable"]
291pub type CountsyncW<'a, REG> = crate::BitWriter<'a, REG>;
292impl R {
293    #[doc = "Bit 0 - Software Reset"]
294    #[inline(always)]
295    pub fn swrst(&self) -> SwrstR {
296        SwrstR::new((self.bits & 1) != 0)
297    }
298    #[doc = "Bit 1 - Enable"]
299    #[inline(always)]
300    pub fn enable(&self) -> EnableR {
301        EnableR::new(((self.bits >> 1) & 1) != 0)
302    }
303    #[doc = "Bits 2:3 - Operating Mode"]
304    #[inline(always)]
305    pub fn mode(&self) -> ModeR {
306        ModeR::new(((self.bits >> 2) & 3) as u8)
307    }
308    #[doc = "Bit 7 - Clear on Match"]
309    #[inline(always)]
310    pub fn matchclr(&self) -> MatchclrR {
311        MatchclrR::new(((self.bits >> 7) & 1) != 0)
312    }
313    #[doc = "Bits 8:11 - Prescaler"]
314    #[inline(always)]
315    pub fn prescaler(&self) -> PrescalerR {
316        PrescalerR::new(((self.bits >> 8) & 0x0f) as u8)
317    }
318    #[doc = "Bit 13 - BKUP Registers Reset On Tamper Enable"]
319    #[inline(always)]
320    pub fn bktrst(&self) -> BktrstR {
321        BktrstR::new(((self.bits >> 13) & 1) != 0)
322    }
323    #[doc = "Bit 14 - GP Registers Reset On Tamper Enable"]
324    #[inline(always)]
325    pub fn gptrst(&self) -> GptrstR {
326        GptrstR::new(((self.bits >> 14) & 1) != 0)
327    }
328    #[doc = "Bit 15 - Count Read Synchronization Enable"]
329    #[inline(always)]
330    pub fn countsync(&self) -> CountsyncR {
331        CountsyncR::new(((self.bits >> 15) & 1) != 0)
332    }
333}
334impl W {
335    #[doc = "Bit 0 - Software Reset"]
336    #[inline(always)]
337    #[must_use]
338    pub fn swrst(&mut self) -> SwrstW<CtrlaSpec> {
339        SwrstW::new(self, 0)
340    }
341    #[doc = "Bit 1 - Enable"]
342    #[inline(always)]
343    #[must_use]
344    pub fn enable(&mut self) -> EnableW<CtrlaSpec> {
345        EnableW::new(self, 1)
346    }
347    #[doc = "Bits 2:3 - Operating Mode"]
348    #[inline(always)]
349    #[must_use]
350    pub fn mode(&mut self) -> ModeW<CtrlaSpec> {
351        ModeW::new(self, 2)
352    }
353    #[doc = "Bit 7 - Clear on Match"]
354    #[inline(always)]
355    #[must_use]
356    pub fn matchclr(&mut self) -> MatchclrW<CtrlaSpec> {
357        MatchclrW::new(self, 7)
358    }
359    #[doc = "Bits 8:11 - Prescaler"]
360    #[inline(always)]
361    #[must_use]
362    pub fn prescaler(&mut self) -> PrescalerW<CtrlaSpec> {
363        PrescalerW::new(self, 8)
364    }
365    #[doc = "Bit 13 - BKUP Registers Reset On Tamper Enable"]
366    #[inline(always)]
367    #[must_use]
368    pub fn bktrst(&mut self) -> BktrstW<CtrlaSpec> {
369        BktrstW::new(self, 13)
370    }
371    #[doc = "Bit 14 - GP Registers Reset On Tamper Enable"]
372    #[inline(always)]
373    #[must_use]
374    pub fn gptrst(&mut self) -> GptrstW<CtrlaSpec> {
375        GptrstW::new(self, 14)
376    }
377    #[doc = "Bit 15 - Count Read Synchronization Enable"]
378    #[inline(always)]
379    #[must_use]
380    pub fn countsync(&mut self) -> CountsyncW<CtrlaSpec> {
381        CountsyncW::new(self, 15)
382    }
383}
384#[doc = "MODE0 Control A\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrla::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrla::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
385pub struct CtrlaSpec;
386impl crate::RegisterSpec for CtrlaSpec {
387    type Ux = u16;
388}
389#[doc = "`read()` method returns [`ctrla::R`](R) reader structure"]
390impl crate::Readable for CtrlaSpec {}
391#[doc = "`write(|w| ..)` method takes [`ctrla::W`](W) writer structure"]
392impl crate::Writable for CtrlaSpec {
393    type Safety = crate::Unsafe;
394    const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0;
395    const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0;
396}
397#[doc = "`reset()` method sets CTRLA to value 0"]
398impl crate::Resettable for CtrlaSpec {
399    const RESET_VALUE: u16 = 0;
400}
atsamd51j/rtc/mode0/ctrla.rs

atsamd51j/rtc/mode0/
ctrla.rs
