atsamd51j/tc0/count16/
intenclr.rs

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1#[doc = "Register `INTENCLR` reader"]
2pub type R = crate::R<IntenclrSpec>;
3#[doc = "Register `INTENCLR` writer"]
4pub type W = crate::W<IntenclrSpec>;
5#[doc = "Field `OVF` reader - OVF Interrupt Disable"]
6pub type OvfR = crate::BitReader;
7#[doc = "Field `OVF` writer - OVF Interrupt Disable"]
8pub type OvfW<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `ERR` reader - ERR Interrupt Disable"]
10pub type ErrR = crate::BitReader;
11#[doc = "Field `ERR` writer - ERR Interrupt Disable"]
12pub type ErrW<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `MC0` reader - MC Interrupt Disable 0"]
14pub type Mc0R = crate::BitReader;
15#[doc = "Field `MC0` writer - MC Interrupt Disable 0"]
16pub type Mc0W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `MC1` reader - MC Interrupt Disable 1"]
18pub type Mc1R = crate::BitReader;
19#[doc = "Field `MC1` writer - MC Interrupt Disable 1"]
20pub type Mc1W<'a, REG> = crate::BitWriter<'a, REG>;
21impl R {
22    #[doc = "Bit 0 - OVF Interrupt Disable"]
23    #[inline(always)]
24    pub fn ovf(&self) -> OvfR {
25        OvfR::new((self.bits & 1) != 0)
26    }
27    #[doc = "Bit 1 - ERR Interrupt Disable"]
28    #[inline(always)]
29    pub fn err(&self) -> ErrR {
30        ErrR::new(((self.bits >> 1) & 1) != 0)
31    }
32    #[doc = "Bit 4 - MC Interrupt Disable 0"]
33    #[inline(always)]
34    pub fn mc0(&self) -> Mc0R {
35        Mc0R::new(((self.bits >> 4) & 1) != 0)
36    }
37    #[doc = "Bit 5 - MC Interrupt Disable 1"]
38    #[inline(always)]
39    pub fn mc1(&self) -> Mc1R {
40        Mc1R::new(((self.bits >> 5) & 1) != 0)
41    }
42}
43impl W {
44    #[doc = "Bit 0 - OVF Interrupt Disable"]
45    #[inline(always)]
46    #[must_use]
47    pub fn ovf(&mut self) -> OvfW<IntenclrSpec> {
48        OvfW::new(self, 0)
49    }
50    #[doc = "Bit 1 - ERR Interrupt Disable"]
51    #[inline(always)]
52    #[must_use]
53    pub fn err(&mut self) -> ErrW<IntenclrSpec> {
54        ErrW::new(self, 1)
55    }
56    #[doc = "Bit 4 - MC Interrupt Disable 0"]
57    #[inline(always)]
58    #[must_use]
59    pub fn mc0(&mut self) -> Mc0W<IntenclrSpec> {
60        Mc0W::new(self, 4)
61    }
62    #[doc = "Bit 5 - MC Interrupt Disable 1"]
63    #[inline(always)]
64    #[must_use]
65    pub fn mc1(&mut self) -> Mc1W<IntenclrSpec> {
66        Mc1W::new(self, 5)
67    }
68}
69#[doc = "Interrupt Enable Clear\n\nYou can [`read`](crate::Reg::read) this register and get [`intenclr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intenclr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
70pub struct IntenclrSpec;
71impl crate::RegisterSpec for IntenclrSpec {
72    type Ux = u8;
73}
74#[doc = "`read()` method returns [`intenclr::R`](R) reader structure"]
75impl crate::Readable for IntenclrSpec {}
76#[doc = "`write(|w| ..)` method takes [`intenclr::W`](W) writer structure"]
77impl crate::Writable for IntenclrSpec {
78    type Safety = crate::Unsafe;
79    const ZERO_TO_MODIFY_FIELDS_BITMAP: u8 = 0;
80    const ONE_TO_MODIFY_FIELDS_BITMAP: u8 = 0;
81}
82#[doc = "`reset()` method sets INTENCLR to value 0"]
83impl crate::Resettable for IntenclrSpec {
84    const RESET_VALUE: u8 = 0;
85}
atsamd51j/tc0/count16/intenclr.rs

atsamd51j/tc0/count16/
intenclr.rs
