atsamd51j/oscctrl/dpll/
dpllsyncbusy.rs

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1#[doc = "Register `DPLLSYNCBUSY` reader"]
2pub type R = crate::R<DpllsyncbusySpec>;
3#[doc = "Field `ENABLE` reader - DPLL Enable Synchronization Status"]
4pub type EnableR = crate::BitReader;
5#[doc = "Field `DPLLRATIO` reader - DPLL Loop Divider Ratio Synchronization Status"]
6pub type DpllratioR = crate::BitReader;
7impl R {
8    #[doc = "Bit 1 - DPLL Enable Synchronization Status"]
9    #[inline(always)]
10    pub fn enable(&self) -> EnableR {
11        EnableR::new(((self.bits >> 1) & 1) != 0)
12    }
13    #[doc = "Bit 2 - DPLL Loop Divider Ratio Synchronization Status"]
14    #[inline(always)]
15    pub fn dpllratio(&self) -> DpllratioR {
16        DpllratioR::new(((self.bits >> 2) & 1) != 0)
17    }
18}
19#[doc = "DPLL Synchronization Busy\n\nYou can [`read`](crate::Reg::read) this register and get [`dpllsyncbusy::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
20pub struct DpllsyncbusySpec;
21impl crate::RegisterSpec for DpllsyncbusySpec {
22    type Ux = u32;
23}
24#[doc = "`read()` method returns [`dpllsyncbusy::R`](R) reader structure"]
25impl crate::Readable for DpllsyncbusySpec {}
26#[doc = "`reset()` method sets DPLLSYNCBUSY to value 0"]
27impl crate::Resettable for DpllsyncbusySpec {
28    const RESET_VALUE: u32 = 0;
29}
atsamd51j/oscctrl/dpll/dpllsyncbusy.rs

atsamd51j/oscctrl/dpll/
dpllsyncbusy.rs
