atsamd51j/tcc0/
intenclr.rs

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1#[doc = "Register `INTENCLR` reader"]
2pub type R = crate::R<IntenclrSpec>;
3#[doc = "Register `INTENCLR` writer"]
4pub type W = crate::W<IntenclrSpec>;
5#[doc = "Field `OVF` reader - Overflow Interrupt Enable"]
6pub type OvfR = crate::BitReader;
7#[doc = "Field `OVF` writer - Overflow Interrupt Enable"]
8pub type OvfW<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `TRG` reader - Retrigger Interrupt Enable"]
10pub type TrgR = crate::BitReader;
11#[doc = "Field `TRG` writer - Retrigger Interrupt Enable"]
12pub type TrgW<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `CNT` reader - Counter Interrupt Enable"]
14pub type CntR = crate::BitReader;
15#[doc = "Field `CNT` writer - Counter Interrupt Enable"]
16pub type CntW<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `ERR` reader - Error Interrupt Enable"]
18pub type ErrR = crate::BitReader;
19#[doc = "Field `ERR` writer - Error Interrupt Enable"]
20pub type ErrW<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `UFS` reader - Non-Recoverable Update Fault Interrupt Enable"]
22pub type UfsR = crate::BitReader;
23#[doc = "Field `UFS` writer - Non-Recoverable Update Fault Interrupt Enable"]
24pub type UfsW<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `DFS` reader - Non-Recoverable Debug Fault Interrupt Enable"]
26pub type DfsR = crate::BitReader;
27#[doc = "Field `DFS` writer - Non-Recoverable Debug Fault Interrupt Enable"]
28pub type DfsW<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `FAULTA` reader - Recoverable Fault A Interrupt Enable"]
30pub type FaultaR = crate::BitReader;
31#[doc = "Field `FAULTA` writer - Recoverable Fault A Interrupt Enable"]
32pub type FaultaW<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `FAULTB` reader - Recoverable Fault B Interrupt Enable"]
34pub type FaultbR = crate::BitReader;
35#[doc = "Field `FAULTB` writer - Recoverable Fault B Interrupt Enable"]
36pub type FaultbW<'a, REG> = crate::BitWriter<'a, REG>;
37#[doc = "Field `FAULT0` reader - Non-Recoverable Fault 0 Interrupt Enable"]
38pub type Fault0R = crate::BitReader;
39#[doc = "Field `FAULT0` writer - Non-Recoverable Fault 0 Interrupt Enable"]
40pub type Fault0W<'a, REG> = crate::BitWriter<'a, REG>;
41#[doc = "Field `FAULT1` reader - Non-Recoverable Fault 1 Interrupt Enable"]
42pub type Fault1R = crate::BitReader;
43#[doc = "Field `FAULT1` writer - Non-Recoverable Fault 1 Interrupt Enable"]
44pub type Fault1W<'a, REG> = crate::BitWriter<'a, REG>;
45#[doc = "Field `MC0` reader - Match or Capture Channel 0 Interrupt Enable"]
46pub type Mc0R = crate::BitReader;
47#[doc = "Field `MC0` writer - Match or Capture Channel 0 Interrupt Enable"]
48pub type Mc0W<'a, REG> = crate::BitWriter<'a, REG>;
49#[doc = "Field `MC1` reader - Match or Capture Channel 1 Interrupt Enable"]
50pub type Mc1R = crate::BitReader;
51#[doc = "Field `MC1` writer - Match or Capture Channel 1 Interrupt Enable"]
52pub type Mc1W<'a, REG> = crate::BitWriter<'a, REG>;
53#[doc = "Field `MC2` reader - Match or Capture Channel 2 Interrupt Enable"]
54pub type Mc2R = crate::BitReader;
55#[doc = "Field `MC2` writer - Match or Capture Channel 2 Interrupt Enable"]
56pub type Mc2W<'a, REG> = crate::BitWriter<'a, REG>;
57#[doc = "Field `MC3` reader - Match or Capture Channel 3 Interrupt Enable"]
58pub type Mc3R = crate::BitReader;
59#[doc = "Field `MC3` writer - Match or Capture Channel 3 Interrupt Enable"]
60pub type Mc3W<'a, REG> = crate::BitWriter<'a, REG>;
61#[doc = "Field `MC4` reader - Match or Capture Channel 4 Interrupt Enable"]
62pub type Mc4R = crate::BitReader;
63#[doc = "Field `MC4` writer - Match or Capture Channel 4 Interrupt Enable"]
64pub type Mc4W<'a, REG> = crate::BitWriter<'a, REG>;
65#[doc = "Field `MC5` reader - Match or Capture Channel 5 Interrupt Enable"]
66pub type Mc5R = crate::BitReader;
67#[doc = "Field `MC5` writer - Match or Capture Channel 5 Interrupt Enable"]
68pub type Mc5W<'a, REG> = crate::BitWriter<'a, REG>;
69impl R {
70    #[doc = "Bit 0 - Overflow Interrupt Enable"]
71    #[inline(always)]
72    pub fn ovf(&self) -> OvfR {
73        OvfR::new((self.bits & 1) != 0)
74    }
75    #[doc = "Bit 1 - Retrigger Interrupt Enable"]
76    #[inline(always)]
77    pub fn trg(&self) -> TrgR {
78        TrgR::new(((self.bits >> 1) & 1) != 0)
79    }
80    #[doc = "Bit 2 - Counter Interrupt Enable"]
81    #[inline(always)]
82    pub fn cnt(&self) -> CntR {
83        CntR::new(((self.bits >> 2) & 1) != 0)
84    }
85    #[doc = "Bit 3 - Error Interrupt Enable"]
86    #[inline(always)]
87    pub fn err(&self) -> ErrR {
88        ErrR::new(((self.bits >> 3) & 1) != 0)
89    }
90    #[doc = "Bit 10 - Non-Recoverable Update Fault Interrupt Enable"]
91    #[inline(always)]
92    pub fn ufs(&self) -> UfsR {
93        UfsR::new(((self.bits >> 10) & 1) != 0)
94    }
95    #[doc = "Bit 11 - Non-Recoverable Debug Fault Interrupt Enable"]
96    #[inline(always)]
97    pub fn dfs(&self) -> DfsR {
98        DfsR::new(((self.bits >> 11) & 1) != 0)
99    }
100    #[doc = "Bit 12 - Recoverable Fault A Interrupt Enable"]
101    #[inline(always)]
102    pub fn faulta(&self) -> FaultaR {
103        FaultaR::new(((self.bits >> 12) & 1) != 0)
104    }
105    #[doc = "Bit 13 - Recoverable Fault B Interrupt Enable"]
106    #[inline(always)]
107    pub fn faultb(&self) -> FaultbR {
108        FaultbR::new(((self.bits >> 13) & 1) != 0)
109    }
110    #[doc = "Bit 14 - Non-Recoverable Fault 0 Interrupt Enable"]
111    #[inline(always)]
112    pub fn fault0(&self) -> Fault0R {
113        Fault0R::new(((self.bits >> 14) & 1) != 0)
114    }
115    #[doc = "Bit 15 - Non-Recoverable Fault 1 Interrupt Enable"]
116    #[inline(always)]
117    pub fn fault1(&self) -> Fault1R {
118        Fault1R::new(((self.bits >> 15) & 1) != 0)
119    }
120    #[doc = "Bit 16 - Match or Capture Channel 0 Interrupt Enable"]
121    #[inline(always)]
122    pub fn mc0(&self) -> Mc0R {
123        Mc0R::new(((self.bits >> 16) & 1) != 0)
124    }
125    #[doc = "Bit 17 - Match or Capture Channel 1 Interrupt Enable"]
126    #[inline(always)]
127    pub fn mc1(&self) -> Mc1R {
128        Mc1R::new(((self.bits >> 17) & 1) != 0)
129    }
130    #[doc = "Bit 18 - Match or Capture Channel 2 Interrupt Enable"]
131    #[inline(always)]
132    pub fn mc2(&self) -> Mc2R {
133        Mc2R::new(((self.bits >> 18) & 1) != 0)
134    }
135    #[doc = "Bit 19 - Match or Capture Channel 3 Interrupt Enable"]
136    #[inline(always)]
137    pub fn mc3(&self) -> Mc3R {
138        Mc3R::new(((self.bits >> 19) & 1) != 0)
139    }
140    #[doc = "Bit 20 - Match or Capture Channel 4 Interrupt Enable"]
141    #[inline(always)]
142    pub fn mc4(&self) -> Mc4R {
143        Mc4R::new(((self.bits >> 20) & 1) != 0)
144    }
145    #[doc = "Bit 21 - Match or Capture Channel 5 Interrupt Enable"]
146    #[inline(always)]
147    pub fn mc5(&self) -> Mc5R {
148        Mc5R::new(((self.bits >> 21) & 1) != 0)
149    }
150}
151impl W {
152    #[doc = "Bit 0 - Overflow Interrupt Enable"]
153    #[inline(always)]
154    #[must_use]
155    pub fn ovf(&mut self) -> OvfW<IntenclrSpec> {
156        OvfW::new(self, 0)
157    }
158    #[doc = "Bit 1 - Retrigger Interrupt Enable"]
159    #[inline(always)]
160    #[must_use]
161    pub fn trg(&mut self) -> TrgW<IntenclrSpec> {
162        TrgW::new(self, 1)
163    }
164    #[doc = "Bit 2 - Counter Interrupt Enable"]
165    #[inline(always)]
166    #[must_use]
167    pub fn cnt(&mut self) -> CntW<IntenclrSpec> {
168        CntW::new(self, 2)
169    }
170    #[doc = "Bit 3 - Error Interrupt Enable"]
171    #[inline(always)]
172    #[must_use]
173    pub fn err(&mut self) -> ErrW<IntenclrSpec> {
174        ErrW::new(self, 3)
175    }
176    #[doc = "Bit 10 - Non-Recoverable Update Fault Interrupt Enable"]
177    #[inline(always)]
178    #[must_use]
179    pub fn ufs(&mut self) -> UfsW<IntenclrSpec> {
180        UfsW::new(self, 10)
181    }
182    #[doc = "Bit 11 - Non-Recoverable Debug Fault Interrupt Enable"]
183    #[inline(always)]
184    #[must_use]
185    pub fn dfs(&mut self) -> DfsW<IntenclrSpec> {
186        DfsW::new(self, 11)
187    }
188    #[doc = "Bit 12 - Recoverable Fault A Interrupt Enable"]
189    #[inline(always)]
190    #[must_use]
191    pub fn faulta(&mut self) -> FaultaW<IntenclrSpec> {
192        FaultaW::new(self, 12)
193    }
194    #[doc = "Bit 13 - Recoverable Fault B Interrupt Enable"]
195    #[inline(always)]
196    #[must_use]
197    pub fn faultb(&mut self) -> FaultbW<IntenclrSpec> {
198        FaultbW::new(self, 13)
199    }
200    #[doc = "Bit 14 - Non-Recoverable Fault 0 Interrupt Enable"]
201    #[inline(always)]
202    #[must_use]
203    pub fn fault0(&mut self) -> Fault0W<IntenclrSpec> {
204        Fault0W::new(self, 14)
205    }
206    #[doc = "Bit 15 - Non-Recoverable Fault 1 Interrupt Enable"]
207    #[inline(always)]
208    #[must_use]
209    pub fn fault1(&mut self) -> Fault1W<IntenclrSpec> {
210        Fault1W::new(self, 15)
211    }
212    #[doc = "Bit 16 - Match or Capture Channel 0 Interrupt Enable"]
213    #[inline(always)]
214    #[must_use]
215    pub fn mc0(&mut self) -> Mc0W<IntenclrSpec> {
216        Mc0W::new(self, 16)
217    }
218    #[doc = "Bit 17 - Match or Capture Channel 1 Interrupt Enable"]
219    #[inline(always)]
220    #[must_use]
221    pub fn mc1(&mut self) -> Mc1W<IntenclrSpec> {
222        Mc1W::new(self, 17)
223    }
224    #[doc = "Bit 18 - Match or Capture Channel 2 Interrupt Enable"]
225    #[inline(always)]
226    #[must_use]
227    pub fn mc2(&mut self) -> Mc2W<IntenclrSpec> {
228        Mc2W::new(self, 18)
229    }
230    #[doc = "Bit 19 - Match or Capture Channel 3 Interrupt Enable"]
231    #[inline(always)]
232    #[must_use]
233    pub fn mc3(&mut self) -> Mc3W<IntenclrSpec> {
234        Mc3W::new(self, 19)
235    }
236    #[doc = "Bit 20 - Match or Capture Channel 4 Interrupt Enable"]
237    #[inline(always)]
238    #[must_use]
239    pub fn mc4(&mut self) -> Mc4W<IntenclrSpec> {
240        Mc4W::new(self, 20)
241    }
242    #[doc = "Bit 21 - Match or Capture Channel 5 Interrupt Enable"]
243    #[inline(always)]
244    #[must_use]
245    pub fn mc5(&mut self) -> Mc5W<IntenclrSpec> {
246        Mc5W::new(self, 21)
247    }
248}
249#[doc = "Interrupt Enable Clear\n\nYou can [`read`](crate::Reg::read) this register and get [`intenclr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intenclr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
250pub struct IntenclrSpec;
251impl crate::RegisterSpec for IntenclrSpec {
252    type Ux = u32;
253}
254#[doc = "`read()` method returns [`intenclr::R`](R) reader structure"]
255impl crate::Readable for IntenclrSpec {}
256#[doc = "`write(|w| ..)` method takes [`intenclr::W`](W) writer structure"]
257impl crate::Writable for IntenclrSpec {
258    type Safety = crate::Unsafe;
259    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
260    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
261}
262#[doc = "`reset()` method sets INTENCLR to value 0"]
263impl crate::Resettable for IntenclrSpec {
264    const RESET_VALUE: u32 = 0;
265}
atsamd51j/tcc0/intenclr.rs

atsamd51j/tcc0/
intenclr.rs
