atsamd51j/system_control/
ccr.rs

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1#[doc = "Register `CCR` reader"]
2pub type R = crate::R<CcrSpec>;
3#[doc = "Register `CCR` writer"]
4pub type W = crate::W<CcrSpec>;
5#[doc = "Field `NONBASETHRDENA` reader - Indicates how processor enters Thread mode"]
6pub type NonbasethrdenaR = crate::BitReader;
7#[doc = "Field `NONBASETHRDENA` writer - Indicates how processor enters Thread mode"]
8pub type NonbasethrdenaW<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `USERSETMPEND` reader - Enables unprivileged software access to STIR register"]
10pub type UsersetmpendR = crate::BitReader;
11#[doc = "Field `USERSETMPEND` writer - Enables unprivileged software access to STIR register"]
12pub type UsersetmpendW<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Enables unaligned access traps\n\nValue on reset: 0"]
14#[derive(Clone, Copy, Debug, PartialEq, Eq)]
15pub enum UnalignTrpselect {
16    #[doc = "0: Do not trap unaligned halfword and word accesses"]
17    Value0 = 0,
18    #[doc = "1: Trap unaligned halfword and word accesses"]
19    Value1 = 1,
20}
21impl From<UnalignTrpselect> for bool {
22    #[inline(always)]
23    fn from(variant: UnalignTrpselect) -> Self {
24        variant as u8 != 0
25    }
26}
27#[doc = "Field `UNALIGN_TRP` reader - Enables unaligned access traps"]
28pub type UnalignTrpR = crate::BitReader<UnalignTrpselect>;
29impl UnalignTrpR {
30    #[doc = "Get enumerated values variant"]
31    #[inline(always)]
32    pub const fn variant(&self) -> UnalignTrpselect {
33        match self.bits {
34            false => UnalignTrpselect::Value0,
35            true => UnalignTrpselect::Value1,
36        }
37    }
38    #[doc = "Do not trap unaligned halfword and word accesses"]
39    #[inline(always)]
40    pub fn is_value_0(&self) -> bool {
41        *self == UnalignTrpselect::Value0
42    }
43    #[doc = "Trap unaligned halfword and word accesses"]
44    #[inline(always)]
45    pub fn is_value_1(&self) -> bool {
46        *self == UnalignTrpselect::Value1
47    }
48}
49#[doc = "Field `UNALIGN_TRP` writer - Enables unaligned access traps"]
50pub type UnalignTrpW<'a, REG> = crate::BitWriter<'a, REG, UnalignTrpselect>;
51impl<'a, REG> UnalignTrpW<'a, REG>
52where
53    REG: crate::Writable + crate::RegisterSpec,
54{
55    #[doc = "Do not trap unaligned halfword and word accesses"]
56    #[inline(always)]
57    pub fn value_0(self) -> &'a mut crate::W<REG> {
58        self.variant(UnalignTrpselect::Value0)
59    }
60    #[doc = "Trap unaligned halfword and word accesses"]
61    #[inline(always)]
62    pub fn value_1(self) -> &'a mut crate::W<REG> {
63        self.variant(UnalignTrpselect::Value1)
64    }
65}
66#[doc = "Field `DIV_0_TRP` reader - Enables divide by 0 trap"]
67pub type Div0TrpR = crate::BitReader;
68#[doc = "Field `DIV_0_TRP` writer - Enables divide by 0 trap"]
69pub type Div0TrpW<'a, REG> = crate::BitWriter<'a, REG>;
70#[doc = "Field `BFHFNMIGN` reader - Ignore LDM/STM BusFault for -1/-2 priority handlers"]
71pub type BfhfnmignR = crate::BitReader;
72#[doc = "Field `BFHFNMIGN` writer - Ignore LDM/STM BusFault for -1/-2 priority handlers"]
73pub type BfhfnmignW<'a, REG> = crate::BitWriter<'a, REG>;
74#[doc = "Indicates stack alignment on exception entry\n\nValue on reset: 1"]
75#[derive(Clone, Copy, Debug, PartialEq, Eq)]
76pub enum Stkalignselect {
77    #[doc = "0: 4-byte aligned"]
78    Value0 = 0,
79    #[doc = "1: 8-byte aligned"]
80    Value1 = 1,
81}
82impl From<Stkalignselect> for bool {
83    #[inline(always)]
84    fn from(variant: Stkalignselect) -> Self {
85        variant as u8 != 0
86    }
87}
88#[doc = "Field `STKALIGN` reader - Indicates stack alignment on exception entry"]
89pub type StkalignR = crate::BitReader<Stkalignselect>;
90impl StkalignR {
91    #[doc = "Get enumerated values variant"]
92    #[inline(always)]
93    pub const fn variant(&self) -> Stkalignselect {
94        match self.bits {
95            false => Stkalignselect::Value0,
96            true => Stkalignselect::Value1,
97        }
98    }
99    #[doc = "4-byte aligned"]
100    #[inline(always)]
101    pub fn is_value_0(&self) -> bool {
102        *self == Stkalignselect::Value0
103    }
104    #[doc = "8-byte aligned"]
105    #[inline(always)]
106    pub fn is_value_1(&self) -> bool {
107        *self == Stkalignselect::Value1
108    }
109}
110#[doc = "Field `STKALIGN` writer - Indicates stack alignment on exception entry"]
111pub type StkalignW<'a, REG> = crate::BitWriter<'a, REG, Stkalignselect>;
112impl<'a, REG> StkalignW<'a, REG>
113where
114    REG: crate::Writable + crate::RegisterSpec,
115{
116    #[doc = "4-byte aligned"]
117    #[inline(always)]
118    pub fn value_0(self) -> &'a mut crate::W<REG> {
119        self.variant(Stkalignselect::Value0)
120    }
121    #[doc = "8-byte aligned"]
122    #[inline(always)]
123    pub fn value_1(self) -> &'a mut crate::W<REG> {
124        self.variant(Stkalignselect::Value1)
125    }
126}
127impl R {
128    #[doc = "Bit 0 - Indicates how processor enters Thread mode"]
129    #[inline(always)]
130    pub fn nonbasethrdena(&self) -> NonbasethrdenaR {
131        NonbasethrdenaR::new((self.bits & 1) != 0)
132    }
133    #[doc = "Bit 1 - Enables unprivileged software access to STIR register"]
134    #[inline(always)]
135    pub fn usersetmpend(&self) -> UsersetmpendR {
136        UsersetmpendR::new(((self.bits >> 1) & 1) != 0)
137    }
138    #[doc = "Bit 3 - Enables unaligned access traps"]
139    #[inline(always)]
140    pub fn unalign_trp(&self) -> UnalignTrpR {
141        UnalignTrpR::new(((self.bits >> 3) & 1) != 0)
142    }
143    #[doc = "Bit 4 - Enables divide by 0 trap"]
144    #[inline(always)]
145    pub fn div_0_trp(&self) -> Div0TrpR {
146        Div0TrpR::new(((self.bits >> 4) & 1) != 0)
147    }
148    #[doc = "Bit 8 - Ignore LDM/STM BusFault for -1/-2 priority handlers"]
149    #[inline(always)]
150    pub fn bfhfnmign(&self) -> BfhfnmignR {
151        BfhfnmignR::new(((self.bits >> 8) & 1) != 0)
152    }
153    #[doc = "Bit 9 - Indicates stack alignment on exception entry"]
154    #[inline(always)]
155    pub fn stkalign(&self) -> StkalignR {
156        StkalignR::new(((self.bits >> 9) & 1) != 0)
157    }
158}
159impl W {
160    #[doc = "Bit 0 - Indicates how processor enters Thread mode"]
161    #[inline(always)]
162    #[must_use]
163    pub fn nonbasethrdena(&mut self) -> NonbasethrdenaW<CcrSpec> {
164        NonbasethrdenaW::new(self, 0)
165    }
166    #[doc = "Bit 1 - Enables unprivileged software access to STIR register"]
167    #[inline(always)]
168    #[must_use]
169    pub fn usersetmpend(&mut self) -> UsersetmpendW<CcrSpec> {
170        UsersetmpendW::new(self, 1)
171    }
172    #[doc = "Bit 3 - Enables unaligned access traps"]
173    #[inline(always)]
174    #[must_use]
175    pub fn unalign_trp(&mut self) -> UnalignTrpW<CcrSpec> {
176        UnalignTrpW::new(self, 3)
177    }
178    #[doc = "Bit 4 - Enables divide by 0 trap"]
179    #[inline(always)]
180    #[must_use]
181    pub fn div_0_trp(&mut self) -> Div0TrpW<CcrSpec> {
182        Div0TrpW::new(self, 4)
183    }
184    #[doc = "Bit 8 - Ignore LDM/STM BusFault for -1/-2 priority handlers"]
185    #[inline(always)]
186    #[must_use]
187    pub fn bfhfnmign(&mut self) -> BfhfnmignW<CcrSpec> {
188        BfhfnmignW::new(self, 8)
189    }
190    #[doc = "Bit 9 - Indicates stack alignment on exception entry"]
191    #[inline(always)]
192    #[must_use]
193    pub fn stkalign(&mut self) -> StkalignW<CcrSpec> {
194        StkalignW::new(self, 9)
195    }
196}
197#[doc = "Configuration and Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ccr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
198pub struct CcrSpec;
199impl crate::RegisterSpec for CcrSpec {
200    type Ux = u32;
201}
202#[doc = "`read()` method returns [`ccr::R`](R) reader structure"]
203impl crate::Readable for CcrSpec {}
204#[doc = "`write(|w| ..)` method takes [`ccr::W`](W) writer structure"]
205impl crate::Writable for CcrSpec {
206    type Safety = crate::Unsafe;
207    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
208    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
209}
210#[doc = "`reset()` method sets CCR to value 0x0200"]
211impl crate::Resettable for CcrSpec {
212    const RESET_VALUE: u32 = 0x0200;
213}
atsamd51j/system_control/ccr.rs

atsamd51j/system_control/
ccr.rs
