atsamd51j/sdhc0/
tmr.rs

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1#[doc = "Register `TMR` reader"]
2pub type R = crate::R<TmrSpec>;
3#[doc = "Register `TMR` writer"]
4pub type W = crate::W<TmrSpec>;
5#[doc = "DMA Enable\n\nValue on reset: 0"]
6#[derive(Clone, Copy, Debug, PartialEq, Eq)]
7pub enum Dmaenselect {
8    #[doc = "0: No data transfer or Non DMA data transfer"]
9    Disable = 0,
10    #[doc = "1: DMA data transfer"]
11    Enable = 1,
12}
13impl From<Dmaenselect> for bool {
14    #[inline(always)]
15    fn from(variant: Dmaenselect) -> Self {
16        variant as u8 != 0
17    }
18}
19#[doc = "Field `DMAEN` reader - DMA Enable"]
20pub type DmaenR = crate::BitReader<Dmaenselect>;
21impl DmaenR {
22    #[doc = "Get enumerated values variant"]
23    #[inline(always)]
24    pub const fn variant(&self) -> Dmaenselect {
25        match self.bits {
26            false => Dmaenselect::Disable,
27            true => Dmaenselect::Enable,
28        }
29    }
30    #[doc = "No data transfer or Non DMA data transfer"]
31    #[inline(always)]
32    pub fn is_disable(&self) -> bool {
33        *self == Dmaenselect::Disable
34    }
35    #[doc = "DMA data transfer"]
36    #[inline(always)]
37    pub fn is_enable(&self) -> bool {
38        *self == Dmaenselect::Enable
39    }
40}
41#[doc = "Field `DMAEN` writer - DMA Enable"]
42pub type DmaenW<'a, REG> = crate::BitWriter<'a, REG, Dmaenselect>;
43impl<'a, REG> DmaenW<'a, REG>
44where
45    REG: crate::Writable + crate::RegisterSpec,
46{
47    #[doc = "No data transfer or Non DMA data transfer"]
48    #[inline(always)]
49    pub fn disable(self) -> &'a mut crate::W<REG> {
50        self.variant(Dmaenselect::Disable)
51    }
52    #[doc = "DMA data transfer"]
53    #[inline(always)]
54    pub fn enable(self) -> &'a mut crate::W<REG> {
55        self.variant(Dmaenselect::Enable)
56    }
57}
58#[doc = "Block Count Enable\n\nValue on reset: 0"]
59#[derive(Clone, Copy, Debug, PartialEq, Eq)]
60pub enum Bcenselect {
61    #[doc = "0: Disable"]
62    Disable = 0,
63    #[doc = "1: Enable"]
64    Enable = 1,
65}
66impl From<Bcenselect> for bool {
67    #[inline(always)]
68    fn from(variant: Bcenselect) -> Self {
69        variant as u8 != 0
70    }
71}
72#[doc = "Field `BCEN` reader - Block Count Enable"]
73pub type BcenR = crate::BitReader<Bcenselect>;
74impl BcenR {
75    #[doc = "Get enumerated values variant"]
76    #[inline(always)]
77    pub const fn variant(&self) -> Bcenselect {
78        match self.bits {
79            false => Bcenselect::Disable,
80            true => Bcenselect::Enable,
81        }
82    }
83    #[doc = "Disable"]
84    #[inline(always)]
85    pub fn is_disable(&self) -> bool {
86        *self == Bcenselect::Disable
87    }
88    #[doc = "Enable"]
89    #[inline(always)]
90    pub fn is_enable(&self) -> bool {
91        *self == Bcenselect::Enable
92    }
93}
94#[doc = "Field `BCEN` writer - Block Count Enable"]
95pub type BcenW<'a, REG> = crate::BitWriter<'a, REG, Bcenselect>;
96impl<'a, REG> BcenW<'a, REG>
97where
98    REG: crate::Writable + crate::RegisterSpec,
99{
100    #[doc = "Disable"]
101    #[inline(always)]
102    pub fn disable(self) -> &'a mut crate::W<REG> {
103        self.variant(Bcenselect::Disable)
104    }
105    #[doc = "Enable"]
106    #[inline(always)]
107    pub fn enable(self) -> &'a mut crate::W<REG> {
108        self.variant(Bcenselect::Enable)
109    }
110}
111#[doc = "Auto Command Enable\n\nValue on reset: 0"]
112#[derive(Clone, Copy, Debug, PartialEq, Eq)]
113#[repr(u8)]
114pub enum Acmdenselect {
115    #[doc = "0: Auto Command Disabled"]
116    Disabled = 0,
117    #[doc = "1: Auto CMD12 Enable"]
118    Cmd12 = 1,
119    #[doc = "2: Auto CMD23 Enable"]
120    Cmd23 = 2,
121}
122impl From<Acmdenselect> for u8 {
123    #[inline(always)]
124    fn from(variant: Acmdenselect) -> Self {
125        variant as _
126    }
127}
128impl crate::FieldSpec for Acmdenselect {
129    type Ux = u8;
130}
131impl crate::IsEnum for Acmdenselect {}
132#[doc = "Field `ACMDEN` reader - Auto Command Enable"]
133pub type AcmdenR = crate::FieldReader<Acmdenselect>;
134impl AcmdenR {
135    #[doc = "Get enumerated values variant"]
136    #[inline(always)]
137    pub const fn variant(&self) -> Option<Acmdenselect> {
138        match self.bits {
139            0 => Some(Acmdenselect::Disabled),
140            1 => Some(Acmdenselect::Cmd12),
141            2 => Some(Acmdenselect::Cmd23),
142            _ => None,
143        }
144    }
145    #[doc = "Auto Command Disabled"]
146    #[inline(always)]
147    pub fn is_disabled(&self) -> bool {
148        *self == Acmdenselect::Disabled
149    }
150    #[doc = "Auto CMD12 Enable"]
151    #[inline(always)]
152    pub fn is_cmd12(&self) -> bool {
153        *self == Acmdenselect::Cmd12
154    }
155    #[doc = "Auto CMD23 Enable"]
156    #[inline(always)]
157    pub fn is_cmd23(&self) -> bool {
158        *self == Acmdenselect::Cmd23
159    }
160}
161#[doc = "Field `ACMDEN` writer - Auto Command Enable"]
162pub type AcmdenW<'a, REG> = crate::FieldWriter<'a, REG, 2, Acmdenselect>;
163impl<'a, REG> AcmdenW<'a, REG>
164where
165    REG: crate::Writable + crate::RegisterSpec,
166    REG::Ux: From<u8>,
167{
168    #[doc = "Auto Command Disabled"]
169    #[inline(always)]
170    pub fn disabled(self) -> &'a mut crate::W<REG> {
171        self.variant(Acmdenselect::Disabled)
172    }
173    #[doc = "Auto CMD12 Enable"]
174    #[inline(always)]
175    pub fn cmd12(self) -> &'a mut crate::W<REG> {
176        self.variant(Acmdenselect::Cmd12)
177    }
178    #[doc = "Auto CMD23 Enable"]
179    #[inline(always)]
180    pub fn cmd23(self) -> &'a mut crate::W<REG> {
181        self.variant(Acmdenselect::Cmd23)
182    }
183}
184#[doc = "Data Transfer Direction Selection\n\nValue on reset: 0"]
185#[derive(Clone, Copy, Debug, PartialEq, Eq)]
186pub enum Dtdselselect {
187    #[doc = "0: Write (Host to Card)"]
188    Write = 0,
189    #[doc = "1: Read (Card to Host)"]
190    Read = 1,
191}
192impl From<Dtdselselect> for bool {
193    #[inline(always)]
194    fn from(variant: Dtdselselect) -> Self {
195        variant as u8 != 0
196    }
197}
198#[doc = "Field `DTDSEL` reader - Data Transfer Direction Selection"]
199pub type DtdselR = crate::BitReader<Dtdselselect>;
200impl DtdselR {
201    #[doc = "Get enumerated values variant"]
202    #[inline(always)]
203    pub const fn variant(&self) -> Dtdselselect {
204        match self.bits {
205            false => Dtdselselect::Write,
206            true => Dtdselselect::Read,
207        }
208    }
209    #[doc = "Write (Host to Card)"]
210    #[inline(always)]
211    pub fn is_write(&self) -> bool {
212        *self == Dtdselselect::Write
213    }
214    #[doc = "Read (Card to Host)"]
215    #[inline(always)]
216    pub fn is_read(&self) -> bool {
217        *self == Dtdselselect::Read
218    }
219}
220#[doc = "Field `DTDSEL` writer - Data Transfer Direction Selection"]
221pub type DtdselW<'a, REG> = crate::BitWriter<'a, REG, Dtdselselect>;
222impl<'a, REG> DtdselW<'a, REG>
223where
224    REG: crate::Writable + crate::RegisterSpec,
225{
226    #[doc = "Write (Host to Card)"]
227    #[inline(always)]
228    pub fn write(self) -> &'a mut crate::W<REG> {
229        self.variant(Dtdselselect::Write)
230    }
231    #[doc = "Read (Card to Host)"]
232    #[inline(always)]
233    pub fn read(self) -> &'a mut crate::W<REG> {
234        self.variant(Dtdselselect::Read)
235    }
236}
237#[doc = "Multi/Single Block Selection\n\nValue on reset: 0"]
238#[derive(Clone, Copy, Debug, PartialEq, Eq)]
239pub enum Msbselselect {
240    #[doc = "0: Single Block"]
241    Single = 0,
242    #[doc = "1: Multiple Block"]
243    Multiple = 1,
244}
245impl From<Msbselselect> for bool {
246    #[inline(always)]
247    fn from(variant: Msbselselect) -> Self {
248        variant as u8 != 0
249    }
250}
251#[doc = "Field `MSBSEL` reader - Multi/Single Block Selection"]
252pub type MsbselR = crate::BitReader<Msbselselect>;
253impl MsbselR {
254    #[doc = "Get enumerated values variant"]
255    #[inline(always)]
256    pub const fn variant(&self) -> Msbselselect {
257        match self.bits {
258            false => Msbselselect::Single,
259            true => Msbselselect::Multiple,
260        }
261    }
262    #[doc = "Single Block"]
263    #[inline(always)]
264    pub fn is_single(&self) -> bool {
265        *self == Msbselselect::Single
266    }
267    #[doc = "Multiple Block"]
268    #[inline(always)]
269    pub fn is_multiple(&self) -> bool {
270        *self == Msbselselect::Multiple
271    }
272}
273#[doc = "Field `MSBSEL` writer - Multi/Single Block Selection"]
274pub type MsbselW<'a, REG> = crate::BitWriter<'a, REG, Msbselselect>;
275impl<'a, REG> MsbselW<'a, REG>
276where
277    REG: crate::Writable + crate::RegisterSpec,
278{
279    #[doc = "Single Block"]
280    #[inline(always)]
281    pub fn single(self) -> &'a mut crate::W<REG> {
282        self.variant(Msbselselect::Single)
283    }
284    #[doc = "Multiple Block"]
285    #[inline(always)]
286    pub fn multiple(self) -> &'a mut crate::W<REG> {
287        self.variant(Msbselselect::Multiple)
288    }
289}
290impl R {
291    #[doc = "Bit 0 - DMA Enable"]
292    #[inline(always)]
293    pub fn dmaen(&self) -> DmaenR {
294        DmaenR::new((self.bits & 1) != 0)
295    }
296    #[doc = "Bit 1 - Block Count Enable"]
297    #[inline(always)]
298    pub fn bcen(&self) -> BcenR {
299        BcenR::new(((self.bits >> 1) & 1) != 0)
300    }
301    #[doc = "Bits 2:3 - Auto Command Enable"]
302    #[inline(always)]
303    pub fn acmden(&self) -> AcmdenR {
304        AcmdenR::new(((self.bits >> 2) & 3) as u8)
305    }
306    #[doc = "Bit 4 - Data Transfer Direction Selection"]
307    #[inline(always)]
308    pub fn dtdsel(&self) -> DtdselR {
309        DtdselR::new(((self.bits >> 4) & 1) != 0)
310    }
311    #[doc = "Bit 5 - Multi/Single Block Selection"]
312    #[inline(always)]
313    pub fn msbsel(&self) -> MsbselR {
314        MsbselR::new(((self.bits >> 5) & 1) != 0)
315    }
316}
317impl W {
318    #[doc = "Bit 0 - DMA Enable"]
319    #[inline(always)]
320    #[must_use]
321    pub fn dmaen(&mut self) -> DmaenW<TmrSpec> {
322        DmaenW::new(self, 0)
323    }
324    #[doc = "Bit 1 - Block Count Enable"]
325    #[inline(always)]
326    #[must_use]
327    pub fn bcen(&mut self) -> BcenW<TmrSpec> {
328        BcenW::new(self, 1)
329    }
330    #[doc = "Bits 2:3 - Auto Command Enable"]
331    #[inline(always)]
332    #[must_use]
333    pub fn acmden(&mut self) -> AcmdenW<TmrSpec> {
334        AcmdenW::new(self, 2)
335    }
336    #[doc = "Bit 4 - Data Transfer Direction Selection"]
337    #[inline(always)]
338    #[must_use]
339    pub fn dtdsel(&mut self) -> DtdselW<TmrSpec> {
340        DtdselW::new(self, 4)
341    }
342    #[doc = "Bit 5 - Multi/Single Block Selection"]
343    #[inline(always)]
344    #[must_use]
345    pub fn msbsel(&mut self) -> MsbselW<TmrSpec> {
346        MsbselW::new(self, 5)
347    }
348}
349#[doc = "Transfer Mode\n\nYou can [`read`](crate::Reg::read) this register and get [`tmr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tmr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
350pub struct TmrSpec;
351impl crate::RegisterSpec for TmrSpec {
352    type Ux = u16;
353}
354#[doc = "`read()` method returns [`tmr::R`](R) reader structure"]
355impl crate::Readable for TmrSpec {}
356#[doc = "`write(|w| ..)` method takes [`tmr::W`](W) writer structure"]
357impl crate::Writable for TmrSpec {
358    type Safety = crate::Unsafe;
359    const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0;
360    const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0;
361}
362#[doc = "`reset()` method sets TMR to value 0"]
363impl crate::Resettable for TmrSpec {
364    const RESET_VALUE: u16 = 0;
365}
atsamd51j/sdhc0/tmr.rs

atsamd51j/sdhc0/
tmr.rs
