atsamd51j/oscctrl/
intenclr.rs

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1#[doc = "Register `INTENCLR` reader"]
2pub type R = crate::R<IntenclrSpec>;
3#[doc = "Register `INTENCLR` writer"]
4pub type W = crate::W<IntenclrSpec>;
5#[doc = "Field `XOSCRDY0` reader - XOSC 0 Ready Interrupt Enable"]
6pub type Xoscrdy0R = crate::BitReader;
7#[doc = "Field `XOSCRDY0` writer - XOSC 0 Ready Interrupt Enable"]
8pub type Xoscrdy0W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `XOSCRDY1` reader - XOSC 1 Ready Interrupt Enable"]
10pub type Xoscrdy1R = crate::BitReader;
11#[doc = "Field `XOSCRDY1` writer - XOSC 1 Ready Interrupt Enable"]
12pub type Xoscrdy1W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `XOSCFAIL0` reader - XOSC 0 Clock Failure Detector Interrupt Enable"]
14pub type Xoscfail0R = crate::BitReader;
15#[doc = "Field `XOSCFAIL0` writer - XOSC 0 Clock Failure Detector Interrupt Enable"]
16pub type Xoscfail0W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `XOSCFAIL1` reader - XOSC 1 Clock Failure Detector Interrupt Enable"]
18pub type Xoscfail1R = crate::BitReader;
19#[doc = "Field `XOSCFAIL1` writer - XOSC 1 Clock Failure Detector Interrupt Enable"]
20pub type Xoscfail1W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `DFLLRDY` reader - DFLL Ready Interrupt Enable"]
22pub type DfllrdyR = crate::BitReader;
23#[doc = "Field `DFLLRDY` writer - DFLL Ready Interrupt Enable"]
24pub type DfllrdyW<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `DFLLOOB` reader - DFLL Out Of Bounds Interrupt Enable"]
26pub type DflloobR = crate::BitReader;
27#[doc = "Field `DFLLOOB` writer - DFLL Out Of Bounds Interrupt Enable"]
28pub type DflloobW<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `DFLLLCKF` reader - DFLL Lock Fine Interrupt Enable"]
30pub type DflllckfR = crate::BitReader;
31#[doc = "Field `DFLLLCKF` writer - DFLL Lock Fine Interrupt Enable"]
32pub type DflllckfW<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `DFLLLCKC` reader - DFLL Lock Coarse Interrupt Enable"]
34pub type DflllckcR = crate::BitReader;
35#[doc = "Field `DFLLLCKC` writer - DFLL Lock Coarse Interrupt Enable"]
36pub type DflllckcW<'a, REG> = crate::BitWriter<'a, REG>;
37#[doc = "Field `DFLLRCS` reader - DFLL Reference Clock Stopped Interrupt Enable"]
38pub type DfllrcsR = crate::BitReader;
39#[doc = "Field `DFLLRCS` writer - DFLL Reference Clock Stopped Interrupt Enable"]
40pub type DfllrcsW<'a, REG> = crate::BitWriter<'a, REG>;
41#[doc = "Field `DPLL0LCKR` reader - DPLL0 Lock Rise Interrupt Enable"]
42pub type Dpll0lckrR = crate::BitReader;
43#[doc = "Field `DPLL0LCKR` writer - DPLL0 Lock Rise Interrupt Enable"]
44pub type Dpll0lckrW<'a, REG> = crate::BitWriter<'a, REG>;
45#[doc = "Field `DPLL0LCKF` reader - DPLL0 Lock Fall Interrupt Enable"]
46pub type Dpll0lckfR = crate::BitReader;
47#[doc = "Field `DPLL0LCKF` writer - DPLL0 Lock Fall Interrupt Enable"]
48pub type Dpll0lckfW<'a, REG> = crate::BitWriter<'a, REG>;
49#[doc = "Field `DPLL0LTO` reader - DPLL0 Lock Timeout Interrupt Enable"]
50pub type Dpll0ltoR = crate::BitReader;
51#[doc = "Field `DPLL0LTO` writer - DPLL0 Lock Timeout Interrupt Enable"]
52pub type Dpll0ltoW<'a, REG> = crate::BitWriter<'a, REG>;
53#[doc = "Field `DPLL0LDRTO` reader - DPLL0 Loop Divider Ratio Update Complete Interrupt Enable"]
54pub type Dpll0ldrtoR = crate::BitReader;
55#[doc = "Field `DPLL0LDRTO` writer - DPLL0 Loop Divider Ratio Update Complete Interrupt Enable"]
56pub type Dpll0ldrtoW<'a, REG> = crate::BitWriter<'a, REG>;
57#[doc = "Field `DPLL1LCKR` reader - DPLL1 Lock Rise Interrupt Enable"]
58pub type Dpll1lckrR = crate::BitReader;
59#[doc = "Field `DPLL1LCKR` writer - DPLL1 Lock Rise Interrupt Enable"]
60pub type Dpll1lckrW<'a, REG> = crate::BitWriter<'a, REG>;
61#[doc = "Field `DPLL1LCKF` reader - DPLL1 Lock Fall Interrupt Enable"]
62pub type Dpll1lckfR = crate::BitReader;
63#[doc = "Field `DPLL1LCKF` writer - DPLL1 Lock Fall Interrupt Enable"]
64pub type Dpll1lckfW<'a, REG> = crate::BitWriter<'a, REG>;
65#[doc = "Field `DPLL1LTO` reader - DPLL1 Lock Timeout Interrupt Enable"]
66pub type Dpll1ltoR = crate::BitReader;
67#[doc = "Field `DPLL1LTO` writer - DPLL1 Lock Timeout Interrupt Enable"]
68pub type Dpll1ltoW<'a, REG> = crate::BitWriter<'a, REG>;
69#[doc = "Field `DPLL1LDRTO` reader - DPLL1 Loop Divider Ratio Update Complete Interrupt Enable"]
70pub type Dpll1ldrtoR = crate::BitReader;
71#[doc = "Field `DPLL1LDRTO` writer - DPLL1 Loop Divider Ratio Update Complete Interrupt Enable"]
72pub type Dpll1ldrtoW<'a, REG> = crate::BitWriter<'a, REG>;
73impl R {
74    #[doc = "Bit 0 - XOSC 0 Ready Interrupt Enable"]
75    #[inline(always)]
76    pub fn xoscrdy0(&self) -> Xoscrdy0R {
77        Xoscrdy0R::new((self.bits & 1) != 0)
78    }
79    #[doc = "Bit 1 - XOSC 1 Ready Interrupt Enable"]
80    #[inline(always)]
81    pub fn xoscrdy1(&self) -> Xoscrdy1R {
82        Xoscrdy1R::new(((self.bits >> 1) & 1) != 0)
83    }
84    #[doc = "Bit 2 - XOSC 0 Clock Failure Detector Interrupt Enable"]
85    #[inline(always)]
86    pub fn xoscfail0(&self) -> Xoscfail0R {
87        Xoscfail0R::new(((self.bits >> 2) & 1) != 0)
88    }
89    #[doc = "Bit 3 - XOSC 1 Clock Failure Detector Interrupt Enable"]
90    #[inline(always)]
91    pub fn xoscfail1(&self) -> Xoscfail1R {
92        Xoscfail1R::new(((self.bits >> 3) & 1) != 0)
93    }
94    #[doc = "Bit 8 - DFLL Ready Interrupt Enable"]
95    #[inline(always)]
96    pub fn dfllrdy(&self) -> DfllrdyR {
97        DfllrdyR::new(((self.bits >> 8) & 1) != 0)
98    }
99    #[doc = "Bit 9 - DFLL Out Of Bounds Interrupt Enable"]
100    #[inline(always)]
101    pub fn dflloob(&self) -> DflloobR {
102        DflloobR::new(((self.bits >> 9) & 1) != 0)
103    }
104    #[doc = "Bit 10 - DFLL Lock Fine Interrupt Enable"]
105    #[inline(always)]
106    pub fn dflllckf(&self) -> DflllckfR {
107        DflllckfR::new(((self.bits >> 10) & 1) != 0)
108    }
109    #[doc = "Bit 11 - DFLL Lock Coarse Interrupt Enable"]
110    #[inline(always)]
111    pub fn dflllckc(&self) -> DflllckcR {
112        DflllckcR::new(((self.bits >> 11) & 1) != 0)
113    }
114    #[doc = "Bit 12 - DFLL Reference Clock Stopped Interrupt Enable"]
115    #[inline(always)]
116    pub fn dfllrcs(&self) -> DfllrcsR {
117        DfllrcsR::new(((self.bits >> 12) & 1) != 0)
118    }
119    #[doc = "Bit 16 - DPLL0 Lock Rise Interrupt Enable"]
120    #[inline(always)]
121    pub fn dpll0lckr(&self) -> Dpll0lckrR {
122        Dpll0lckrR::new(((self.bits >> 16) & 1) != 0)
123    }
124    #[doc = "Bit 17 - DPLL0 Lock Fall Interrupt Enable"]
125    #[inline(always)]
126    pub fn dpll0lckf(&self) -> Dpll0lckfR {
127        Dpll0lckfR::new(((self.bits >> 17) & 1) != 0)
128    }
129    #[doc = "Bit 18 - DPLL0 Lock Timeout Interrupt Enable"]
130    #[inline(always)]
131    pub fn dpll0lto(&self) -> Dpll0ltoR {
132        Dpll0ltoR::new(((self.bits >> 18) & 1) != 0)
133    }
134    #[doc = "Bit 19 - DPLL0 Loop Divider Ratio Update Complete Interrupt Enable"]
135    #[inline(always)]
136    pub fn dpll0ldrto(&self) -> Dpll0ldrtoR {
137        Dpll0ldrtoR::new(((self.bits >> 19) & 1) != 0)
138    }
139    #[doc = "Bit 24 - DPLL1 Lock Rise Interrupt Enable"]
140    #[inline(always)]
141    pub fn dpll1lckr(&self) -> Dpll1lckrR {
142        Dpll1lckrR::new(((self.bits >> 24) & 1) != 0)
143    }
144    #[doc = "Bit 25 - DPLL1 Lock Fall Interrupt Enable"]
145    #[inline(always)]
146    pub fn dpll1lckf(&self) -> Dpll1lckfR {
147        Dpll1lckfR::new(((self.bits >> 25) & 1) != 0)
148    }
149    #[doc = "Bit 26 - DPLL1 Lock Timeout Interrupt Enable"]
150    #[inline(always)]
151    pub fn dpll1lto(&self) -> Dpll1ltoR {
152        Dpll1ltoR::new(((self.bits >> 26) & 1) != 0)
153    }
154    #[doc = "Bit 27 - DPLL1 Loop Divider Ratio Update Complete Interrupt Enable"]
155    #[inline(always)]
156    pub fn dpll1ldrto(&self) -> Dpll1ldrtoR {
157        Dpll1ldrtoR::new(((self.bits >> 27) & 1) != 0)
158    }
159}
160impl W {
161    #[doc = "Bit 0 - XOSC 0 Ready Interrupt Enable"]
162    #[inline(always)]
163    #[must_use]
164    pub fn xoscrdy0(&mut self) -> Xoscrdy0W<IntenclrSpec> {
165        Xoscrdy0W::new(self, 0)
166    }
167    #[doc = "Bit 1 - XOSC 1 Ready Interrupt Enable"]
168    #[inline(always)]
169    #[must_use]
170    pub fn xoscrdy1(&mut self) -> Xoscrdy1W<IntenclrSpec> {
171        Xoscrdy1W::new(self, 1)
172    }
173    #[doc = "Bit 2 - XOSC 0 Clock Failure Detector Interrupt Enable"]
174    #[inline(always)]
175    #[must_use]
176    pub fn xoscfail0(&mut self) -> Xoscfail0W<IntenclrSpec> {
177        Xoscfail0W::new(self, 2)
178    }
179    #[doc = "Bit 3 - XOSC 1 Clock Failure Detector Interrupt Enable"]
180    #[inline(always)]
181    #[must_use]
182    pub fn xoscfail1(&mut self) -> Xoscfail1W<IntenclrSpec> {
183        Xoscfail1W::new(self, 3)
184    }
185    #[doc = "Bit 8 - DFLL Ready Interrupt Enable"]
186    #[inline(always)]
187    #[must_use]
188    pub fn dfllrdy(&mut self) -> DfllrdyW<IntenclrSpec> {
189        DfllrdyW::new(self, 8)
190    }
191    #[doc = "Bit 9 - DFLL Out Of Bounds Interrupt Enable"]
192    #[inline(always)]
193    #[must_use]
194    pub fn dflloob(&mut self) -> DflloobW<IntenclrSpec> {
195        DflloobW::new(self, 9)
196    }
197    #[doc = "Bit 10 - DFLL Lock Fine Interrupt Enable"]
198    #[inline(always)]
199    #[must_use]
200    pub fn dflllckf(&mut self) -> DflllckfW<IntenclrSpec> {
201        DflllckfW::new(self, 10)
202    }
203    #[doc = "Bit 11 - DFLL Lock Coarse Interrupt Enable"]
204    #[inline(always)]
205    #[must_use]
206    pub fn dflllckc(&mut self) -> DflllckcW<IntenclrSpec> {
207        DflllckcW::new(self, 11)
208    }
209    #[doc = "Bit 12 - DFLL Reference Clock Stopped Interrupt Enable"]
210    #[inline(always)]
211    #[must_use]
212    pub fn dfllrcs(&mut self) -> DfllrcsW<IntenclrSpec> {
213        DfllrcsW::new(self, 12)
214    }
215    #[doc = "Bit 16 - DPLL0 Lock Rise Interrupt Enable"]
216    #[inline(always)]
217    #[must_use]
218    pub fn dpll0lckr(&mut self) -> Dpll0lckrW<IntenclrSpec> {
219        Dpll0lckrW::new(self, 16)
220    }
221    #[doc = "Bit 17 - DPLL0 Lock Fall Interrupt Enable"]
222    #[inline(always)]
223    #[must_use]
224    pub fn dpll0lckf(&mut self) -> Dpll0lckfW<IntenclrSpec> {
225        Dpll0lckfW::new(self, 17)
226    }
227    #[doc = "Bit 18 - DPLL0 Lock Timeout Interrupt Enable"]
228    #[inline(always)]
229    #[must_use]
230    pub fn dpll0lto(&mut self) -> Dpll0ltoW<IntenclrSpec> {
231        Dpll0ltoW::new(self, 18)
232    }
233    #[doc = "Bit 19 - DPLL0 Loop Divider Ratio Update Complete Interrupt Enable"]
234    #[inline(always)]
235    #[must_use]
236    pub fn dpll0ldrto(&mut self) -> Dpll0ldrtoW<IntenclrSpec> {
237        Dpll0ldrtoW::new(self, 19)
238    }
239    #[doc = "Bit 24 - DPLL1 Lock Rise Interrupt Enable"]
240    #[inline(always)]
241    #[must_use]
242    pub fn dpll1lckr(&mut self) -> Dpll1lckrW<IntenclrSpec> {
243        Dpll1lckrW::new(self, 24)
244    }
245    #[doc = "Bit 25 - DPLL1 Lock Fall Interrupt Enable"]
246    #[inline(always)]
247    #[must_use]
248    pub fn dpll1lckf(&mut self) -> Dpll1lckfW<IntenclrSpec> {
249        Dpll1lckfW::new(self, 25)
250    }
251    #[doc = "Bit 26 - DPLL1 Lock Timeout Interrupt Enable"]
252    #[inline(always)]
253    #[must_use]
254    pub fn dpll1lto(&mut self) -> Dpll1ltoW<IntenclrSpec> {
255        Dpll1ltoW::new(self, 26)
256    }
257    #[doc = "Bit 27 - DPLL1 Loop Divider Ratio Update Complete Interrupt Enable"]
258    #[inline(always)]
259    #[must_use]
260    pub fn dpll1ldrto(&mut self) -> Dpll1ldrtoW<IntenclrSpec> {
261        Dpll1ldrtoW::new(self, 27)
262    }
263}
264#[doc = "Interrupt Enable Clear\n\nYou can [`read`](crate::Reg::read) this register and get [`intenclr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intenclr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
265pub struct IntenclrSpec;
266impl crate::RegisterSpec for IntenclrSpec {
267    type Ux = u32;
268}
269#[doc = "`read()` method returns [`intenclr::R`](R) reader structure"]
270impl crate::Readable for IntenclrSpec {}
271#[doc = "`write(|w| ..)` method takes [`intenclr::W`](W) writer structure"]
272impl crate::Writable for IntenclrSpec {
273    type Safety = crate::Unsafe;
274    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
275    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
276}
277#[doc = "`reset()` method sets INTENCLR to value 0"]
278impl crate::Resettable for IntenclrSpec {
279    const RESET_VALUE: u32 = 0;
280}
atsamd51j/oscctrl/intenclr.rs

atsamd51j/oscctrl/
intenclr.rs
