atsamd51j/osc32kctrl/
intenclr.rs

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1#[doc = "Register `INTENCLR` reader"]
2pub type R = crate::R<IntenclrSpec>;
3#[doc = "Register `INTENCLR` writer"]
4pub type W = crate::W<IntenclrSpec>;
5#[doc = "Field `XOSC32KRDY` reader - XOSC32K Ready Interrupt Enable"]
6pub type Xosc32krdyR = crate::BitReader;
7#[doc = "Field `XOSC32KRDY` writer - XOSC32K Ready Interrupt Enable"]
8pub type Xosc32krdyW<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `XOSC32KFAIL` reader - XOSC32K Clock Failure Detector Interrupt Enable"]
10pub type Xosc32kfailR = crate::BitReader;
11#[doc = "Field `XOSC32KFAIL` writer - XOSC32K Clock Failure Detector Interrupt Enable"]
12pub type Xosc32kfailW<'a, REG> = crate::BitWriter<'a, REG>;
13impl R {
14    #[doc = "Bit 0 - XOSC32K Ready Interrupt Enable"]
15    #[inline(always)]
16    pub fn xosc32krdy(&self) -> Xosc32krdyR {
17        Xosc32krdyR::new((self.bits & 1) != 0)
18    }
19    #[doc = "Bit 2 - XOSC32K Clock Failure Detector Interrupt Enable"]
20    #[inline(always)]
21    pub fn xosc32kfail(&self) -> Xosc32kfailR {
22        Xosc32kfailR::new(((self.bits >> 2) & 1) != 0)
23    }
24}
25impl W {
26    #[doc = "Bit 0 - XOSC32K Ready Interrupt Enable"]
27    #[inline(always)]
28    #[must_use]
29    pub fn xosc32krdy(&mut self) -> Xosc32krdyW<IntenclrSpec> {
30        Xosc32krdyW::new(self, 0)
31    }
32    #[doc = "Bit 2 - XOSC32K Clock Failure Detector Interrupt Enable"]
33    #[inline(always)]
34    #[must_use]
35    pub fn xosc32kfail(&mut self) -> Xosc32kfailW<IntenclrSpec> {
36        Xosc32kfailW::new(self, 2)
37    }
38}
39#[doc = "Interrupt Enable Clear\n\nYou can [`read`](crate::Reg::read) this register and get [`intenclr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intenclr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
40pub struct IntenclrSpec;
41impl crate::RegisterSpec for IntenclrSpec {
42    type Ux = u32;
43}
44#[doc = "`read()` method returns [`intenclr::R`](R) reader structure"]
45impl crate::Readable for IntenclrSpec {}
46#[doc = "`write(|w| ..)` method takes [`intenclr::W`](W) writer structure"]
47impl crate::Writable for IntenclrSpec {
48    type Safety = crate::Unsafe;
49    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
50    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
51}
52#[doc = "`reset()` method sets INTENCLR to value 0"]
53impl crate::Resettable for IntenclrSpec {
54    const RESET_VALUE: u32 = 0;
55}
atsamd51j/osc32kctrl/intenclr.rs

atsamd51j/osc32kctrl/
intenclr.rs
