atsamd51j/dmac/
intpend.rs

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1#[doc = "Register `INTPEND` reader"]
2pub type R = crate::R<IntpendSpec>;
3#[doc = "Register `INTPEND` writer"]
4pub type W = crate::W<IntpendSpec>;
5#[doc = "Field `ID` reader - Channel ID"]
6pub type IdR = crate::FieldReader;
7#[doc = "Field `ID` writer - Channel ID"]
8pub type IdW<'a, REG> = crate::FieldWriter<'a, REG, 5>;
9#[doc = "Field `TERR` reader - Transfer Error"]
10pub type TerrR = crate::BitReader;
11#[doc = "Field `TERR` writer - Transfer Error"]
12pub type TerrW<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `TCMPL` reader - Transfer Complete"]
14pub type TcmplR = crate::BitReader;
15#[doc = "Field `TCMPL` writer - Transfer Complete"]
16pub type TcmplW<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `SUSP` reader - Channel Suspend"]
18pub type SuspR = crate::BitReader;
19#[doc = "Field `SUSP` writer - Channel Suspend"]
20pub type SuspW<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `CRCERR` reader - CRC Error"]
22pub type CrcerrR = crate::BitReader;
23#[doc = "Field `CRCERR` writer - CRC Error"]
24pub type CrcerrW<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `FERR` reader - Fetch Error"]
26pub type FerrR = crate::BitReader;
27#[doc = "Field `FERR` writer - Fetch Error"]
28pub type FerrW<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `BUSY` reader - Busy"]
30pub type BusyR = crate::BitReader;
31#[doc = "Field `BUSY` writer - Busy"]
32pub type BusyW<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `PEND` reader - Pending"]
34pub type PendR = crate::BitReader;
35#[doc = "Field `PEND` writer - Pending"]
36pub type PendW<'a, REG> = crate::BitWriter<'a, REG>;
37impl R {
38    #[doc = "Bits 0:4 - Channel ID"]
39    #[inline(always)]
40    pub fn id(&self) -> IdR {
41        IdR::new((self.bits & 0x1f) as u8)
42    }
43    #[doc = "Bit 8 - Transfer Error"]
44    #[inline(always)]
45    pub fn terr(&self) -> TerrR {
46        TerrR::new(((self.bits >> 8) & 1) != 0)
47    }
48    #[doc = "Bit 9 - Transfer Complete"]
49    #[inline(always)]
50    pub fn tcmpl(&self) -> TcmplR {
51        TcmplR::new(((self.bits >> 9) & 1) != 0)
52    }
53    #[doc = "Bit 10 - Channel Suspend"]
54    #[inline(always)]
55    pub fn susp(&self) -> SuspR {
56        SuspR::new(((self.bits >> 10) & 1) != 0)
57    }
58    #[doc = "Bit 12 - CRC Error"]
59    #[inline(always)]
60    pub fn crcerr(&self) -> CrcerrR {
61        CrcerrR::new(((self.bits >> 12) & 1) != 0)
62    }
63    #[doc = "Bit 13 - Fetch Error"]
64    #[inline(always)]
65    pub fn ferr(&self) -> FerrR {
66        FerrR::new(((self.bits >> 13) & 1) != 0)
67    }
68    #[doc = "Bit 14 - Busy"]
69    #[inline(always)]
70    pub fn busy(&self) -> BusyR {
71        BusyR::new(((self.bits >> 14) & 1) != 0)
72    }
73    #[doc = "Bit 15 - Pending"]
74    #[inline(always)]
75    pub fn pend(&self) -> PendR {
76        PendR::new(((self.bits >> 15) & 1) != 0)
77    }
78}
79impl W {
80    #[doc = "Bits 0:4 - Channel ID"]
81    #[inline(always)]
82    #[must_use]
83    pub fn id(&mut self) -> IdW<IntpendSpec> {
84        IdW::new(self, 0)
85    }
86    #[doc = "Bit 8 - Transfer Error"]
87    #[inline(always)]
88    #[must_use]
89    pub fn terr(&mut self) -> TerrW<IntpendSpec> {
90        TerrW::new(self, 8)
91    }
92    #[doc = "Bit 9 - Transfer Complete"]
93    #[inline(always)]
94    #[must_use]
95    pub fn tcmpl(&mut self) -> TcmplW<IntpendSpec> {
96        TcmplW::new(self, 9)
97    }
98    #[doc = "Bit 10 - Channel Suspend"]
99    #[inline(always)]
100    #[must_use]
101    pub fn susp(&mut self) -> SuspW<IntpendSpec> {
102        SuspW::new(self, 10)
103    }
104    #[doc = "Bit 12 - CRC Error"]
105    #[inline(always)]
106    #[must_use]
107    pub fn crcerr(&mut self) -> CrcerrW<IntpendSpec> {
108        CrcerrW::new(self, 12)
109    }
110    #[doc = "Bit 13 - Fetch Error"]
111    #[inline(always)]
112    #[must_use]
113    pub fn ferr(&mut self) -> FerrW<IntpendSpec> {
114        FerrW::new(self, 13)
115    }
116    #[doc = "Bit 14 - Busy"]
117    #[inline(always)]
118    #[must_use]
119    pub fn busy(&mut self) -> BusyW<IntpendSpec> {
120        BusyW::new(self, 14)
121    }
122    #[doc = "Bit 15 - Pending"]
123    #[inline(always)]
124    #[must_use]
125    pub fn pend(&mut self) -> PendW<IntpendSpec> {
126        PendW::new(self, 15)
127    }
128}
129#[doc = "Interrupt Pending\n\nYou can [`read`](crate::Reg::read) this register and get [`intpend::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intpend::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
130pub struct IntpendSpec;
131impl crate::RegisterSpec for IntpendSpec {
132    type Ux = u16;
133}
134#[doc = "`read()` method returns [`intpend::R`](R) reader structure"]
135impl crate::Readable for IntpendSpec {}
136#[doc = "`write(|w| ..)` method takes [`intpend::W`](W) writer structure"]
137impl crate::Writable for IntpendSpec {
138    type Safety = crate::Unsafe;
139    const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0;
140    const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0;
141}
142#[doc = "`reset()` method sets INTPEND to value 0"]
143impl crate::Resettable for IntpendSpec {
144    const RESET_VALUE: u16 = 0;
145}
atsamd51j/dmac/intpend.rs

atsamd51j/dmac/
intpend.rs
