atsamd21g/usb/
host.rs

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1#[repr(C)]
2#[doc = "USB is Host"]
3#[doc(alias = "HOST")]
4pub struct Host {
5    ctrla: Ctrla,
6    _reserved1: [u8; 0x01],
7    syncbusy: Syncbusy,
8    qosctrl: Qosctrl,
9    _reserved3: [u8; 0x04],
10    ctrlb: Ctrlb,
11    hsofc: Hsofc,
12    _reserved5: [u8; 0x01],
13    status: Status,
14    fsmstatus: Fsmstatus,
15    _reserved7: [u8; 0x02],
16    fnum: Fnum,
17    flenhigh: Flenhigh,
18    _reserved9: [u8; 0x01],
19    intenclr: Intenclr,
20    _reserved10: [u8; 0x02],
21    intenset: Intenset,
22    _reserved11: [u8; 0x02],
23    intflag: Intflag,
24    _reserved12: [u8; 0x02],
25    pintsmry: Pintsmry,
26    _reserved13: [u8; 0x02],
27    descadd: Descadd,
28    padcal: Padcal,
29    _reserved15: [u8; 0xd6],
30    pcfg: (),
31    _reserved16: [u8; 0x03],
32    binterval: (),
33    _reserved17: [u8; 0x01],
34    pstatusclr: (),
35    _reserved18: [u8; 0x01],
36    pstatusset: (),
37    _reserved19: [u8; 0x01],
38    pstatus: (),
39    _reserved20: [u8; 0x01],
40    pintflag: (),
41    _reserved21: [u8; 0x01],
42    pintenclr: (),
43    _reserved22: [u8; 0x01],
44    pintenset: (),
45}
46impl Host {
47    #[doc = "0x00 - Control A"]
48    #[inline(always)]
49    pub const fn ctrla(&self) -> &Ctrla {
50        &self.ctrla
51    }
52    #[doc = "0x02 - Synchronization Busy"]
53    #[inline(always)]
54    pub const fn syncbusy(&self) -> &Syncbusy {
55        &self.syncbusy
56    }
57    #[doc = "0x03 - USB Quality Of Service"]
58    #[inline(always)]
59    pub const fn qosctrl(&self) -> &Qosctrl {
60        &self.qosctrl
61    }
62    #[doc = "0x08 - HOST Control B"]
63    #[inline(always)]
64    pub const fn ctrlb(&self) -> &Ctrlb {
65        &self.ctrlb
66    }
67    #[doc = "0x0a - HOST Host Start Of Frame Control"]
68    #[inline(always)]
69    pub const fn hsofc(&self) -> &Hsofc {
70        &self.hsofc
71    }
72    #[doc = "0x0c - HOST Status"]
73    #[inline(always)]
74    pub const fn status(&self) -> &Status {
75        &self.status
76    }
77    #[doc = "0x0d - Finite State Machine Status"]
78    #[inline(always)]
79    pub const fn fsmstatus(&self) -> &Fsmstatus {
80        &self.fsmstatus
81    }
82    #[doc = "0x10 - HOST Host Frame Number"]
83    #[inline(always)]
84    pub const fn fnum(&self) -> &Fnum {
85        &self.fnum
86    }
87    #[doc = "0x12 - HOST Host Frame Length"]
88    #[inline(always)]
89    pub const fn flenhigh(&self) -> &Flenhigh {
90        &self.flenhigh
91    }
92    #[doc = "0x14 - HOST Host Interrupt Enable Clear"]
93    #[inline(always)]
94    pub const fn intenclr(&self) -> &Intenclr {
95        &self.intenclr
96    }
97    #[doc = "0x18 - HOST Host Interrupt Enable Set"]
98    #[inline(always)]
99    pub const fn intenset(&self) -> &Intenset {
100        &self.intenset
101    }
102    #[doc = "0x1c - HOST Host Interrupt Flag"]
103    #[inline(always)]
104    pub const fn intflag(&self) -> &Intflag {
105        &self.intflag
106    }
107    #[doc = "0x20 - HOST Pipe Interrupt Summary"]
108    #[inline(always)]
109    pub const fn pintsmry(&self) -> &Pintsmry {
110        &self.pintsmry
111    }
112    #[doc = "0x24 - Descriptor Address"]
113    #[inline(always)]
114    pub const fn descadd(&self) -> &Descadd {
115        &self.descadd
116    }
117    #[doc = "0x28 - USB PAD Calibration"]
118    #[inline(always)]
119    pub const fn padcal(&self) -> &Padcal {
120        &self.padcal
121    }
122    #[doc = "0x100..0x108 - HOST End Point Configuration"]
123    #[inline(always)]
124    pub const fn pcfg(&self, n: usize) -> &Pcfg {
125        #[allow(clippy::no_effect)]
126        [(); 8][n];
127        unsafe {
128            &*(self as *const Self)
129                .cast::<u8>()
130                .add(256)
131                .add(32 * n)
132                .cast()
133        }
134    }
135    #[doc = "Iterator for array of:"]
136    #[doc = "0x100..0x108 - HOST End Point Configuration"]
137    #[inline(always)]
138    pub fn pcfg_iter(&self) -> impl Iterator<Item = &Pcfg> {
139        (0..8).map(move |n| unsafe {
140            &*(self as *const Self)
141                .cast::<u8>()
142                .add(256)
143                .add(32 * n)
144                .cast()
145        })
146    }
147    #[doc = "0x103..0x10b - HOST Bus Access Period of Pipe"]
148    #[inline(always)]
149    pub const fn binterval(&self, n: usize) -> &Binterval {
150        #[allow(clippy::no_effect)]
151        [(); 8][n];
152        unsafe {
153            &*(self as *const Self)
154                .cast::<u8>()
155                .add(259)
156                .add(32 * n)
157                .cast()
158        }
159    }
160    #[doc = "Iterator for array of:"]
161    #[doc = "0x103..0x10b - HOST Bus Access Period of Pipe"]
162    #[inline(always)]
163    pub fn binterval_iter(&self) -> impl Iterator<Item = &Binterval> {
164        (0..8).map(move |n| unsafe {
165            &*(self as *const Self)
166                .cast::<u8>()
167                .add(259)
168                .add(32 * n)
169                .cast()
170        })
171    }
172    #[doc = "0x104..0x10c - HOST End Point Pipe Status Clear"]
173    #[inline(always)]
174    pub const fn pstatusclr(&self, n: usize) -> &Pstatusclr {
175        #[allow(clippy::no_effect)]
176        [(); 8][n];
177        unsafe {
178            &*(self as *const Self)
179                .cast::<u8>()
180                .add(260)
181                .add(32 * n)
182                .cast()
183        }
184    }
185    #[doc = "Iterator for array of:"]
186    #[doc = "0x104..0x10c - HOST End Point Pipe Status Clear"]
187    #[inline(always)]
188    pub fn pstatusclr_iter(&self) -> impl Iterator<Item = &Pstatusclr> {
189        (0..8).map(move |n| unsafe {
190            &*(self as *const Self)
191                .cast::<u8>()
192                .add(260)
193                .add(32 * n)
194                .cast()
195        })
196    }
197    #[doc = "0x105..0x10d - HOST End Point Pipe Status Set"]
198    #[inline(always)]
199    pub const fn pstatusset(&self, n: usize) -> &Pstatusset {
200        #[allow(clippy::no_effect)]
201        [(); 8][n];
202        unsafe {
203            &*(self as *const Self)
204                .cast::<u8>()
205                .add(261)
206                .add(32 * n)
207                .cast()
208        }
209    }
210    #[doc = "Iterator for array of:"]
211    #[doc = "0x105..0x10d - HOST End Point Pipe Status Set"]
212    #[inline(always)]
213    pub fn pstatusset_iter(&self) -> impl Iterator<Item = &Pstatusset> {
214        (0..8).map(move |n| unsafe {
215            &*(self as *const Self)
216                .cast::<u8>()
217                .add(261)
218                .add(32 * n)
219                .cast()
220        })
221    }
222    #[doc = "0x106..0x10e - HOST End Point Pipe Status"]
223    #[inline(always)]
224    pub const fn pstatus(&self, n: usize) -> &Pstatus {
225        #[allow(clippy::no_effect)]
226        [(); 8][n];
227        unsafe {
228            &*(self as *const Self)
229                .cast::<u8>()
230                .add(262)
231                .add(32 * n)
232                .cast()
233        }
234    }
235    #[doc = "Iterator for array of:"]
236    #[doc = "0x106..0x10e - HOST End Point Pipe Status"]
237    #[inline(always)]
238    pub fn pstatus_iter(&self) -> impl Iterator<Item = &Pstatus> {
239        (0..8).map(move |n| unsafe {
240            &*(self as *const Self)
241                .cast::<u8>()
242                .add(262)
243                .add(32 * n)
244                .cast()
245        })
246    }
247    #[doc = "0x107..0x10f - HOST Pipe Interrupt Flag"]
248    #[inline(always)]
249    pub const fn pintflag(&self, n: usize) -> &Pintflag {
250        #[allow(clippy::no_effect)]
251        [(); 8][n];
252        unsafe {
253            &*(self as *const Self)
254                .cast::<u8>()
255                .add(263)
256                .add(32 * n)
257                .cast()
258        }
259    }
260    #[doc = "Iterator for array of:"]
261    #[doc = "0x107..0x10f - HOST Pipe Interrupt Flag"]
262    #[inline(always)]
263    pub fn pintflag_iter(&self) -> impl Iterator<Item = &Pintflag> {
264        (0..8).map(move |n| unsafe {
265            &*(self as *const Self)
266                .cast::<u8>()
267                .add(263)
268                .add(32 * n)
269                .cast()
270        })
271    }
272    #[doc = "0x108..0x110 - HOST Pipe Interrupt Flag Clear"]
273    #[inline(always)]
274    pub const fn pintenclr(&self, n: usize) -> &Pintenclr {
275        #[allow(clippy::no_effect)]
276        [(); 8][n];
277        unsafe {
278            &*(self as *const Self)
279                .cast::<u8>()
280                .add(264)
281                .add(32 * n)
282                .cast()
283        }
284    }
285    #[doc = "Iterator for array of:"]
286    #[doc = "0x108..0x110 - HOST Pipe Interrupt Flag Clear"]
287    #[inline(always)]
288    pub fn pintenclr_iter(&self) -> impl Iterator<Item = &Pintenclr> {
289        (0..8).map(move |n| unsafe {
290            &*(self as *const Self)
291                .cast::<u8>()
292                .add(264)
293                .add(32 * n)
294                .cast()
295        })
296    }
297    #[doc = "0x109..0x111 - HOST Pipe Interrupt Flag Set"]
298    #[inline(always)]
299    pub const fn pintenset(&self, n: usize) -> &Pintenset {
300        #[allow(clippy::no_effect)]
301        [(); 8][n];
302        unsafe {
303            &*(self as *const Self)
304                .cast::<u8>()
305                .add(265)
306                .add(32 * n)
307                .cast()
308        }
309    }
310    #[doc = "Iterator for array of:"]
311    #[doc = "0x109..0x111 - HOST Pipe Interrupt Flag Set"]
312    #[inline(always)]
313    pub fn pintenset_iter(&self) -> impl Iterator<Item = &Pintenset> {
314        (0..8).map(move |n| unsafe {
315            &*(self as *const Self)
316                .cast::<u8>()
317                .add(265)
318                .add(32 * n)
319                .cast()
320        })
321    }
322}
323#[doc = "CTRLA (rw) register accessor: Control A\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrla::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrla::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrla`]
324module"]
325#[doc(alias = "CTRLA")]
326pub type Ctrla = crate::Reg<ctrla::CtrlaSpec>;
327#[doc = "Control A"]
328pub mod ctrla;
329#[doc = "SYNCBUSY (r) register accessor: Synchronization Busy\n\nYou can [`read`](crate::Reg::read) this register and get [`syncbusy::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@syncbusy`]
330module"]
331#[doc(alias = "SYNCBUSY")]
332pub type Syncbusy = crate::Reg<syncbusy::SyncbusySpec>;
333#[doc = "Synchronization Busy"]
334pub mod syncbusy;
335#[doc = "QOSCTRL (rw) register accessor: USB Quality Of Service\n\nYou can [`read`](crate::Reg::read) this register and get [`qosctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qosctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qosctrl`]
336module"]
337#[doc(alias = "QOSCTRL")]
338pub type Qosctrl = crate::Reg<qosctrl::QosctrlSpec>;
339#[doc = "USB Quality Of Service"]
340pub mod qosctrl;
341#[doc = "CTRLB (rw) register accessor: HOST Control B\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrlb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrlb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrlb`]
342module"]
343#[doc(alias = "CTRLB")]
344pub type Ctrlb = crate::Reg<ctrlb::CtrlbSpec>;
345#[doc = "HOST Control B"]
346pub mod ctrlb;
347#[doc = "HSOFC (rw) register accessor: HOST Host Start Of Frame Control\n\nYou can [`read`](crate::Reg::read) this register and get [`hsofc::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hsofc::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hsofc`]
348module"]
349#[doc(alias = "HSOFC")]
350pub type Hsofc = crate::Reg<hsofc::HsofcSpec>;
351#[doc = "HOST Host Start Of Frame Control"]
352pub mod hsofc;
353#[doc = "STATUS (rw) register accessor: HOST Status\n\nYou can [`read`](crate::Reg::read) this register and get [`status::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`status::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@status`]
354module"]
355#[doc(alias = "STATUS")]
356pub type Status = crate::Reg<status::StatusSpec>;
357#[doc = "HOST Status"]
358pub mod status;
359#[doc = "FSMSTATUS (r) register accessor: Finite State Machine Status\n\nYou can [`read`](crate::Reg::read) this register and get [`fsmstatus::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fsmstatus`]
360module"]
361#[doc(alias = "FSMSTATUS")]
362pub type Fsmstatus = crate::Reg<fsmstatus::FsmstatusSpec>;
363#[doc = "Finite State Machine Status"]
364pub mod fsmstatus;
365#[doc = "FNUM (rw) register accessor: HOST Host Frame Number\n\nYou can [`read`](crate::Reg::read) this register and get [`fnum::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fnum::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fnum`]
366module"]
367#[doc(alias = "FNUM")]
368pub type Fnum = crate::Reg<fnum::FnumSpec>;
369#[doc = "HOST Host Frame Number"]
370pub mod fnum;
371#[doc = "FLENHIGH (r) register accessor: HOST Host Frame Length\n\nYou can [`read`](crate::Reg::read) this register and get [`flenhigh::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@flenhigh`]
372module"]
373#[doc(alias = "FLENHIGH")]
374pub type Flenhigh = crate::Reg<flenhigh::FlenhighSpec>;
375#[doc = "HOST Host Frame Length"]
376pub mod flenhigh;
377#[doc = "INTENCLR (rw) register accessor: HOST Host Interrupt Enable Clear\n\nYou can [`read`](crate::Reg::read) this register and get [`intenclr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intenclr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intenclr`]
378module"]
379#[doc(alias = "INTENCLR")]
380pub type Intenclr = crate::Reg<intenclr::IntenclrSpec>;
381#[doc = "HOST Host Interrupt Enable Clear"]
382pub mod intenclr;
383#[doc = "INTENSET (rw) register accessor: HOST Host Interrupt Enable Set\n\nYou can [`read`](crate::Reg::read) this register and get [`intenset::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intenset::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intenset`]
384module"]
385#[doc(alias = "INTENSET")]
386pub type Intenset = crate::Reg<intenset::IntensetSpec>;
387#[doc = "HOST Host Interrupt Enable Set"]
388pub mod intenset;
389#[doc = "INTFLAG (rw) register accessor: HOST Host Interrupt Flag\n\nYou can [`read`](crate::Reg::read) this register and get [`intflag::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intflag::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intflag`]
390module"]
391#[doc(alias = "INTFLAG")]
392pub type Intflag = crate::Reg<intflag::IntflagSpec>;
393#[doc = "HOST Host Interrupt Flag"]
394pub mod intflag;
395#[doc = "PINTSMRY (r) register accessor: HOST Pipe Interrupt Summary\n\nYou can [`read`](crate::Reg::read) this register and get [`pintsmry::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pintsmry`]
396module"]
397#[doc(alias = "PINTSMRY")]
398pub type Pintsmry = crate::Reg<pintsmry::PintsmrySpec>;
399#[doc = "HOST Pipe Interrupt Summary"]
400pub mod pintsmry;
401#[doc = "DESCADD (rw) register accessor: Descriptor Address\n\nYou can [`read`](crate::Reg::read) this register and get [`descadd::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`descadd::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@descadd`]
402module"]
403#[doc(alias = "DESCADD")]
404pub type Descadd = crate::Reg<descadd::DescaddSpec>;
405#[doc = "Descriptor Address"]
406pub mod descadd;
407#[doc = "PADCAL (rw) register accessor: USB PAD Calibration\n\nYou can [`read`](crate::Reg::read) this register and get [`padcal::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`padcal::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcal`]
408module"]
409#[doc(alias = "PADCAL")]
410pub type Padcal = crate::Reg<padcal::PadcalSpec>;
411#[doc = "USB PAD Calibration"]
412pub mod padcal;
413#[doc = "PCFG (rw) register accessor: HOST End Point Configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`pcfg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcfg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcfg`]
414module"]
415#[doc(alias = "PCFG")]
416pub type Pcfg = crate::Reg<pcfg::PcfgSpec>;
417#[doc = "HOST End Point Configuration"]
418pub mod pcfg;
419#[doc = "BINTERVAL (rw) register accessor: HOST Bus Access Period of Pipe\n\nYou can [`read`](crate::Reg::read) this register and get [`binterval::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`binterval::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@binterval`]
420module"]
421#[doc(alias = "BINTERVAL")]
422pub type Binterval = crate::Reg<binterval::BintervalSpec>;
423#[doc = "HOST Bus Access Period of Pipe"]
424pub mod binterval;
425#[doc = "PSTATUSCLR (rw) register accessor: HOST End Point Pipe Status Clear\n\nYou can [`read`](crate::Reg::read) this register and get [`pstatusclr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pstatusclr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pstatusclr`]
426module"]
427#[doc(alias = "PSTATUSCLR")]
428pub type Pstatusclr = crate::Reg<pstatusclr::PstatusclrSpec>;
429#[doc = "HOST End Point Pipe Status Clear"]
430pub mod pstatusclr;
431#[doc = "PSTATUSSET (w) register accessor: HOST End Point Pipe Status Set\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pstatusset::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pstatusset`]
432module"]
433#[doc(alias = "PSTATUSSET")]
434pub type Pstatusset = crate::Reg<pstatusset::PstatussetSpec>;
435#[doc = "HOST End Point Pipe Status Set"]
436pub mod pstatusset;
437#[doc = "PSTATUS (r) register accessor: HOST End Point Pipe Status\n\nYou can [`read`](crate::Reg::read) this register and get [`pstatus::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pstatus`]
438module"]
439#[doc(alias = "PSTATUS")]
440pub type Pstatus = crate::Reg<pstatus::PstatusSpec>;
441#[doc = "HOST End Point Pipe Status"]
442pub mod pstatus;
443#[doc = "PINTFLAG (rw) register accessor: HOST Pipe Interrupt Flag\n\nYou can [`read`](crate::Reg::read) this register and get [`pintflag::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pintflag::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pintflag`]
444module"]
445#[doc(alias = "PINTFLAG")]
446pub type Pintflag = crate::Reg<pintflag::PintflagSpec>;
447#[doc = "HOST Pipe Interrupt Flag"]
448pub mod pintflag;
449#[doc = "PINTENCLR (rw) register accessor: HOST Pipe Interrupt Flag Clear\n\nYou can [`read`](crate::Reg::read) this register and get [`pintenclr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pintenclr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pintenclr`]
450module"]
451#[doc(alias = "PINTENCLR")]
452pub type Pintenclr = crate::Reg<pintenclr::PintenclrSpec>;
453#[doc = "HOST Pipe Interrupt Flag Clear"]
454pub mod pintenclr;
455#[doc = "PINTENSET (rw) register accessor: HOST Pipe Interrupt Flag Set\n\nYou can [`read`](crate::Reg::read) this register and get [`pintenset::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pintenset::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pintenset`]
456module"]
457#[doc(alias = "PINTENSET")]
458pub type Pintenset = crate::Reg<pintenset::PintensetSpec>;
459#[doc = "HOST Pipe Interrupt Flag Set"]
460pub mod pintenset;
atsamd21g/usb/host.rs

atsamd21g/usb/
host.rs
