atsamd21g/tcc0/
intenclr.rs

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1#[doc = "Register `INTENCLR` reader"]
2pub type R = crate::R<IntenclrSpec>;
3#[doc = "Register `INTENCLR` writer"]
4pub type W = crate::W<IntenclrSpec>;
5#[doc = "Field `OVF` reader - Overflow Interrupt Enable"]
6pub type OvfR = crate::BitReader;
7#[doc = "Field `OVF` writer - Overflow Interrupt Enable"]
8pub type OvfW<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `TRG` reader - Retrigger Interrupt Enable"]
10pub type TrgR = crate::BitReader;
11#[doc = "Field `TRG` writer - Retrigger Interrupt Enable"]
12pub type TrgW<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `CNT` reader - Counter Interrupt Enable"]
14pub type CntR = crate::BitReader;
15#[doc = "Field `CNT` writer - Counter Interrupt Enable"]
16pub type CntW<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `ERR` reader - Error Interrupt Enable"]
18pub type ErrR = crate::BitReader;
19#[doc = "Field `ERR` writer - Error Interrupt Enable"]
20pub type ErrW<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `DFS` reader - Non-Recoverable Debug Fault Interrupt Enable"]
22pub type DfsR = crate::BitReader;
23#[doc = "Field `DFS` writer - Non-Recoverable Debug Fault Interrupt Enable"]
24pub type DfsW<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `FAULTA` reader - Recoverable Fault A Interrupt Enable"]
26pub type FaultaR = crate::BitReader;
27#[doc = "Field `FAULTA` writer - Recoverable Fault A Interrupt Enable"]
28pub type FaultaW<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `FAULTB` reader - Recoverable Fault B Interrupt Enable"]
30pub type FaultbR = crate::BitReader;
31#[doc = "Field `FAULTB` writer - Recoverable Fault B Interrupt Enable"]
32pub type FaultbW<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `FAULT0` reader - Non-Recoverable Fault 0 Interrupt Enable"]
34pub type Fault0R = crate::BitReader;
35#[doc = "Field `FAULT0` writer - Non-Recoverable Fault 0 Interrupt Enable"]
36pub type Fault0W<'a, REG> = crate::BitWriter<'a, REG>;
37#[doc = "Field `FAULT1` reader - Non-Recoverable Fault 1 Interrupt Enable"]
38pub type Fault1R = crate::BitReader;
39#[doc = "Field `FAULT1` writer - Non-Recoverable Fault 1 Interrupt Enable"]
40pub type Fault1W<'a, REG> = crate::BitWriter<'a, REG>;
41#[doc = "Field `MC0` reader - Match or Capture Channel 0 Interrupt Enable"]
42pub type Mc0R = crate::BitReader;
43#[doc = "Field `MC0` writer - Match or Capture Channel 0 Interrupt Enable"]
44pub type Mc0W<'a, REG> = crate::BitWriter<'a, REG>;
45#[doc = "Field `MC1` reader - Match or Capture Channel 1 Interrupt Enable"]
46pub type Mc1R = crate::BitReader;
47#[doc = "Field `MC1` writer - Match or Capture Channel 1 Interrupt Enable"]
48pub type Mc1W<'a, REG> = crate::BitWriter<'a, REG>;
49#[doc = "Field `MC2` reader - Match or Capture Channel 2 Interrupt Enable"]
50pub type Mc2R = crate::BitReader;
51#[doc = "Field `MC2` writer - Match or Capture Channel 2 Interrupt Enable"]
52pub type Mc2W<'a, REG> = crate::BitWriter<'a, REG>;
53#[doc = "Field `MC3` reader - Match or Capture Channel 3 Interrupt Enable"]
54pub type Mc3R = crate::BitReader;
55#[doc = "Field `MC3` writer - Match or Capture Channel 3 Interrupt Enable"]
56pub type Mc3W<'a, REG> = crate::BitWriter<'a, REG>;
57impl R {
58    #[doc = "Bit 0 - Overflow Interrupt Enable"]
59    #[inline(always)]
60    pub fn ovf(&self) -> OvfR {
61        OvfR::new((self.bits & 1) != 0)
62    }
63    #[doc = "Bit 1 - Retrigger Interrupt Enable"]
64    #[inline(always)]
65    pub fn trg(&self) -> TrgR {
66        TrgR::new(((self.bits >> 1) & 1) != 0)
67    }
68    #[doc = "Bit 2 - Counter Interrupt Enable"]
69    #[inline(always)]
70    pub fn cnt(&self) -> CntR {
71        CntR::new(((self.bits >> 2) & 1) != 0)
72    }
73    #[doc = "Bit 3 - Error Interrupt Enable"]
74    #[inline(always)]
75    pub fn err(&self) -> ErrR {
76        ErrR::new(((self.bits >> 3) & 1) != 0)
77    }
78    #[doc = "Bit 11 - Non-Recoverable Debug Fault Interrupt Enable"]
79    #[inline(always)]
80    pub fn dfs(&self) -> DfsR {
81        DfsR::new(((self.bits >> 11) & 1) != 0)
82    }
83    #[doc = "Bit 12 - Recoverable Fault A Interrupt Enable"]
84    #[inline(always)]
85    pub fn faulta(&self) -> FaultaR {
86        FaultaR::new(((self.bits >> 12) & 1) != 0)
87    }
88    #[doc = "Bit 13 - Recoverable Fault B Interrupt Enable"]
89    #[inline(always)]
90    pub fn faultb(&self) -> FaultbR {
91        FaultbR::new(((self.bits >> 13) & 1) != 0)
92    }
93    #[doc = "Bit 14 - Non-Recoverable Fault 0 Interrupt Enable"]
94    #[inline(always)]
95    pub fn fault0(&self) -> Fault0R {
96        Fault0R::new(((self.bits >> 14) & 1) != 0)
97    }
98    #[doc = "Bit 15 - Non-Recoverable Fault 1 Interrupt Enable"]
99    #[inline(always)]
100    pub fn fault1(&self) -> Fault1R {
101        Fault1R::new(((self.bits >> 15) & 1) != 0)
102    }
103    #[doc = "Bit 16 - Match or Capture Channel 0 Interrupt Enable"]
104    #[inline(always)]
105    pub fn mc0(&self) -> Mc0R {
106        Mc0R::new(((self.bits >> 16) & 1) != 0)
107    }
108    #[doc = "Bit 17 - Match or Capture Channel 1 Interrupt Enable"]
109    #[inline(always)]
110    pub fn mc1(&self) -> Mc1R {
111        Mc1R::new(((self.bits >> 17) & 1) != 0)
112    }
113    #[doc = "Bit 18 - Match or Capture Channel 2 Interrupt Enable"]
114    #[inline(always)]
115    pub fn mc2(&self) -> Mc2R {
116        Mc2R::new(((self.bits >> 18) & 1) != 0)
117    }
118    #[doc = "Bit 19 - Match or Capture Channel 3 Interrupt Enable"]
119    #[inline(always)]
120    pub fn mc3(&self) -> Mc3R {
121        Mc3R::new(((self.bits >> 19) & 1) != 0)
122    }
123}
124impl W {
125    #[doc = "Bit 0 - Overflow Interrupt Enable"]
126    #[inline(always)]
127    #[must_use]
128    pub fn ovf(&mut self) -> OvfW<IntenclrSpec> {
129        OvfW::new(self, 0)
130    }
131    #[doc = "Bit 1 - Retrigger Interrupt Enable"]
132    #[inline(always)]
133    #[must_use]
134    pub fn trg(&mut self) -> TrgW<IntenclrSpec> {
135        TrgW::new(self, 1)
136    }
137    #[doc = "Bit 2 - Counter Interrupt Enable"]
138    #[inline(always)]
139    #[must_use]
140    pub fn cnt(&mut self) -> CntW<IntenclrSpec> {
141        CntW::new(self, 2)
142    }
143    #[doc = "Bit 3 - Error Interrupt Enable"]
144    #[inline(always)]
145    #[must_use]
146    pub fn err(&mut self) -> ErrW<IntenclrSpec> {
147        ErrW::new(self, 3)
148    }
149    #[doc = "Bit 11 - Non-Recoverable Debug Fault Interrupt Enable"]
150    #[inline(always)]
151    #[must_use]
152    pub fn dfs(&mut self) -> DfsW<IntenclrSpec> {
153        DfsW::new(self, 11)
154    }
155    #[doc = "Bit 12 - Recoverable Fault A Interrupt Enable"]
156    #[inline(always)]
157    #[must_use]
158    pub fn faulta(&mut self) -> FaultaW<IntenclrSpec> {
159        FaultaW::new(self, 12)
160    }
161    #[doc = "Bit 13 - Recoverable Fault B Interrupt Enable"]
162    #[inline(always)]
163    #[must_use]
164    pub fn faultb(&mut self) -> FaultbW<IntenclrSpec> {
165        FaultbW::new(self, 13)
166    }
167    #[doc = "Bit 14 - Non-Recoverable Fault 0 Interrupt Enable"]
168    #[inline(always)]
169    #[must_use]
170    pub fn fault0(&mut self) -> Fault0W<IntenclrSpec> {
171        Fault0W::new(self, 14)
172    }
173    #[doc = "Bit 15 - Non-Recoverable Fault 1 Interrupt Enable"]
174    #[inline(always)]
175    #[must_use]
176    pub fn fault1(&mut self) -> Fault1W<IntenclrSpec> {
177        Fault1W::new(self, 15)
178    }
179    #[doc = "Bit 16 - Match or Capture Channel 0 Interrupt Enable"]
180    #[inline(always)]
181    #[must_use]
182    pub fn mc0(&mut self) -> Mc0W<IntenclrSpec> {
183        Mc0W::new(self, 16)
184    }
185    #[doc = "Bit 17 - Match or Capture Channel 1 Interrupt Enable"]
186    #[inline(always)]
187    #[must_use]
188    pub fn mc1(&mut self) -> Mc1W<IntenclrSpec> {
189        Mc1W::new(self, 17)
190    }
191    #[doc = "Bit 18 - Match or Capture Channel 2 Interrupt Enable"]
192    #[inline(always)]
193    #[must_use]
194    pub fn mc2(&mut self) -> Mc2W<IntenclrSpec> {
195        Mc2W::new(self, 18)
196    }
197    #[doc = "Bit 19 - Match or Capture Channel 3 Interrupt Enable"]
198    #[inline(always)]
199    #[must_use]
200    pub fn mc3(&mut self) -> Mc3W<IntenclrSpec> {
201        Mc3W::new(self, 19)
202    }
203}
204#[doc = "Interrupt Enable Clear\n\nYou can [`read`](crate::Reg::read) this register and get [`intenclr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intenclr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
205pub struct IntenclrSpec;
206impl crate::RegisterSpec for IntenclrSpec {
207    type Ux = u32;
208}
209#[doc = "`read()` method returns [`intenclr::R`](R) reader structure"]
210impl crate::Readable for IntenclrSpec {}
211#[doc = "`write(|w| ..)` method takes [`intenclr::W`](W) writer structure"]
212impl crate::Writable for IntenclrSpec {
213    type Safety = crate::Unsafe;
214    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
215    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
216}
217#[doc = "`reset()` method sets INTENCLR to value 0"]
218impl crate::Resettable for IntenclrSpec {
219    const RESET_VALUE: u32 = 0;
220}
atsamd21g/tcc0/intenclr.rs

atsamd21g/tcc0/
intenclr.rs
