atsamd21g/sercom0/i2cm/
status.rs

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1#[doc = "Register `STATUS` reader"]
2pub type R = crate::R<StatusSpec>;
3#[doc = "Register `STATUS` writer"]
4pub type W = crate::W<StatusSpec>;
5#[doc = "Field `BUSERR` reader - Bus Error"]
6pub type BuserrR = crate::BitReader;
7#[doc = "Field `BUSERR` writer - Bus Error"]
8pub type BuserrW<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `ARBLOST` reader - Arbitration Lost"]
10pub type ArblostR = crate::BitReader;
11#[doc = "Field `ARBLOST` writer - Arbitration Lost"]
12pub type ArblostW<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `RXNACK` reader - Received Not Acknowledge"]
14pub type RxnackR = crate::BitReader;
15#[doc = "Field `BUSSTATE` reader - Bus State"]
16pub type BusstateR = crate::FieldReader;
17#[doc = "Field `BUSSTATE` writer - Bus State"]
18pub type BusstateW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
19#[doc = "Field `LOWTOUT` reader - SCL Low Timeout"]
20pub type LowtoutR = crate::BitReader;
21#[doc = "Field `LOWTOUT` writer - SCL Low Timeout"]
22pub type LowtoutW<'a, REG> = crate::BitWriter<'a, REG>;
23#[doc = "Field `CLKHOLD` reader - Clock Hold"]
24pub type ClkholdR = crate::BitReader;
25#[doc = "Field `MEXTTOUT` reader - Master SCL Low Extend Timeout"]
26pub type MexttoutR = crate::BitReader;
27#[doc = "Field `MEXTTOUT` writer - Master SCL Low Extend Timeout"]
28pub type MexttoutW<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `SEXTTOUT` reader - Slave SCL Low Extend Timeout"]
30pub type SexttoutR = crate::BitReader;
31#[doc = "Field `SEXTTOUT` writer - Slave SCL Low Extend Timeout"]
32pub type SexttoutW<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `LENERR` reader - Length Error"]
34pub type LenerrR = crate::BitReader;
35#[doc = "Field `LENERR` writer - Length Error"]
36pub type LenerrW<'a, REG> = crate::BitWriter<'a, REG>;
37impl R {
38    #[doc = "Bit 0 - Bus Error"]
39    #[inline(always)]
40    pub fn buserr(&self) -> BuserrR {
41        BuserrR::new((self.bits & 1) != 0)
42    }
43    #[doc = "Bit 1 - Arbitration Lost"]
44    #[inline(always)]
45    pub fn arblost(&self) -> ArblostR {
46        ArblostR::new(((self.bits >> 1) & 1) != 0)
47    }
48    #[doc = "Bit 2 - Received Not Acknowledge"]
49    #[inline(always)]
50    pub fn rxnack(&self) -> RxnackR {
51        RxnackR::new(((self.bits >> 2) & 1) != 0)
52    }
53    #[doc = "Bits 4:5 - Bus State"]
54    #[inline(always)]
55    pub fn busstate(&self) -> BusstateR {
56        BusstateR::new(((self.bits >> 4) & 3) as u8)
57    }
58    #[doc = "Bit 6 - SCL Low Timeout"]
59    #[inline(always)]
60    pub fn lowtout(&self) -> LowtoutR {
61        LowtoutR::new(((self.bits >> 6) & 1) != 0)
62    }
63    #[doc = "Bit 7 - Clock Hold"]
64    #[inline(always)]
65    pub fn clkhold(&self) -> ClkholdR {
66        ClkholdR::new(((self.bits >> 7) & 1) != 0)
67    }
68    #[doc = "Bit 8 - Master SCL Low Extend Timeout"]
69    #[inline(always)]
70    pub fn mexttout(&self) -> MexttoutR {
71        MexttoutR::new(((self.bits >> 8) & 1) != 0)
72    }
73    #[doc = "Bit 9 - Slave SCL Low Extend Timeout"]
74    #[inline(always)]
75    pub fn sexttout(&self) -> SexttoutR {
76        SexttoutR::new(((self.bits >> 9) & 1) != 0)
77    }
78    #[doc = "Bit 10 - Length Error"]
79    #[inline(always)]
80    pub fn lenerr(&self) -> LenerrR {
81        LenerrR::new(((self.bits >> 10) & 1) != 0)
82    }
83}
84impl W {
85    #[doc = "Bit 0 - Bus Error"]
86    #[inline(always)]
87    #[must_use]
88    pub fn buserr(&mut self) -> BuserrW<StatusSpec> {
89        BuserrW::new(self, 0)
90    }
91    #[doc = "Bit 1 - Arbitration Lost"]
92    #[inline(always)]
93    #[must_use]
94    pub fn arblost(&mut self) -> ArblostW<StatusSpec> {
95        ArblostW::new(self, 1)
96    }
97    #[doc = "Bits 4:5 - Bus State"]
98    #[inline(always)]
99    #[must_use]
100    pub fn busstate(&mut self) -> BusstateW<StatusSpec> {
101        BusstateW::new(self, 4)
102    }
103    #[doc = "Bit 6 - SCL Low Timeout"]
104    #[inline(always)]
105    #[must_use]
106    pub fn lowtout(&mut self) -> LowtoutW<StatusSpec> {
107        LowtoutW::new(self, 6)
108    }
109    #[doc = "Bit 8 - Master SCL Low Extend Timeout"]
110    #[inline(always)]
111    #[must_use]
112    pub fn mexttout(&mut self) -> MexttoutW<StatusSpec> {
113        MexttoutW::new(self, 8)
114    }
115    #[doc = "Bit 9 - Slave SCL Low Extend Timeout"]
116    #[inline(always)]
117    #[must_use]
118    pub fn sexttout(&mut self) -> SexttoutW<StatusSpec> {
119        SexttoutW::new(self, 9)
120    }
121    #[doc = "Bit 10 - Length Error"]
122    #[inline(always)]
123    #[must_use]
124    pub fn lenerr(&mut self) -> LenerrW<StatusSpec> {
125        LenerrW::new(self, 10)
126    }
127}
128#[doc = "I2CM Status\n\nYou can [`read`](crate::Reg::read) this register and get [`status::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`status::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
129pub struct StatusSpec;
130impl crate::RegisterSpec for StatusSpec {
131    type Ux = u16;
132}
133#[doc = "`read()` method returns [`status::R`](R) reader structure"]
134impl crate::Readable for StatusSpec {}
135#[doc = "`write(|w| ..)` method takes [`status::W`](W) writer structure"]
136impl crate::Writable for StatusSpec {
137    type Safety = crate::Unsafe;
138    const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0;
139    const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0;
140}
141#[doc = "`reset()` method sets STATUS to value 0"]
142impl crate::Resettable for StatusSpec {
143    const RESET_VALUE: u16 = 0;
144}
atsamd21g/sercom0/i2cm/status.rs

atsamd21g/sercom0/i2cm/
status.rs
