atsamd21g/adc/
inputctrl.rs

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1#[doc = "Register `INPUTCTRL` reader"]
2pub type R = crate::R<InputctrlSpec>;
3#[doc = "Register `INPUTCTRL` writer"]
4pub type W = crate::W<InputctrlSpec>;
5#[doc = "Positive Mux Input Selection\n\nValue on reset: 0"]
6#[derive(Clone, Copy, Debug, PartialEq, Eq)]
7#[repr(u8)]
8pub enum Muxposselect {
9    #[doc = "0: ADC AIN0 Pin"]
10    Pin0 = 0,
11    #[doc = "1: ADC AIN1 Pin"]
12    Pin1 = 1,
13    #[doc = "2: ADC AIN2 Pin"]
14    Pin2 = 2,
15    #[doc = "3: ADC AIN3 Pin"]
16    Pin3 = 3,
17    #[doc = "4: ADC AIN4 Pin"]
18    Pin4 = 4,
19    #[doc = "5: ADC AIN5 Pin"]
20    Pin5 = 5,
21    #[doc = "6: ADC AIN6 Pin"]
22    Pin6 = 6,
23    #[doc = "7: ADC AIN7 Pin"]
24    Pin7 = 7,
25    #[doc = "8: ADC AIN8 Pin"]
26    Pin8 = 8,
27    #[doc = "9: ADC AIN9 Pin"]
28    Pin9 = 9,
29    #[doc = "10: ADC AIN10 Pin"]
30    Pin10 = 10,
31    #[doc = "11: ADC AIN11 Pin"]
32    Pin11 = 11,
33    #[doc = "12: ADC AIN12 Pin"]
34    Pin12 = 12,
35    #[doc = "13: ADC AIN13 Pin"]
36    Pin13 = 13,
37    #[doc = "14: ADC AIN14 Pin"]
38    Pin14 = 14,
39    #[doc = "15: ADC AIN15 Pin"]
40    Pin15 = 15,
41    #[doc = "16: ADC AIN16 Pin"]
42    Pin16 = 16,
43    #[doc = "17: ADC AIN17 Pin"]
44    Pin17 = 17,
45    #[doc = "18: ADC AIN18 Pin"]
46    Pin18 = 18,
47    #[doc = "19: ADC AIN19 Pin"]
48    Pin19 = 19,
49    #[doc = "24: Temperature Reference"]
50    Temp = 24,
51    #[doc = "25: Bandgap Voltage"]
52    Bandgap = 25,
53    #[doc = "26: 1/4 Scaled Core Supply"]
54    Scaledcorevcc = 26,
55    #[doc = "27: 1/4 Scaled I/O Supply"]
56    Scalediovcc = 27,
57    #[doc = "28: DAC Output"]
58    Dac = 28,
59}
60impl From<Muxposselect> for u8 {
61    #[inline(always)]
62    fn from(variant: Muxposselect) -> Self {
63        variant as _
64    }
65}
66impl crate::FieldSpec for Muxposselect {
67    type Ux = u8;
68}
69impl crate::IsEnum for Muxposselect {}
70#[doc = "Field `MUXPOS` reader - Positive Mux Input Selection"]
71pub type MuxposR = crate::FieldReader<Muxposselect>;
72impl MuxposR {
73    #[doc = "Get enumerated values variant"]
74    #[inline(always)]
75    pub const fn variant(&self) -> Option<Muxposselect> {
76        match self.bits {
77            0 => Some(Muxposselect::Pin0),
78            1 => Some(Muxposselect::Pin1),
79            2 => Some(Muxposselect::Pin2),
80            3 => Some(Muxposselect::Pin3),
81            4 => Some(Muxposselect::Pin4),
82            5 => Some(Muxposselect::Pin5),
83            6 => Some(Muxposselect::Pin6),
84            7 => Some(Muxposselect::Pin7),
85            8 => Some(Muxposselect::Pin8),
86            9 => Some(Muxposselect::Pin9),
87            10 => Some(Muxposselect::Pin10),
88            11 => Some(Muxposselect::Pin11),
89            12 => Some(Muxposselect::Pin12),
90            13 => Some(Muxposselect::Pin13),
91            14 => Some(Muxposselect::Pin14),
92            15 => Some(Muxposselect::Pin15),
93            16 => Some(Muxposselect::Pin16),
94            17 => Some(Muxposselect::Pin17),
95            18 => Some(Muxposselect::Pin18),
96            19 => Some(Muxposselect::Pin19),
97            24 => Some(Muxposselect::Temp),
98            25 => Some(Muxposselect::Bandgap),
99            26 => Some(Muxposselect::Scaledcorevcc),
100            27 => Some(Muxposselect::Scalediovcc),
101            28 => Some(Muxposselect::Dac),
102            _ => None,
103        }
104    }
105    #[doc = "ADC AIN0 Pin"]
106    #[inline(always)]
107    pub fn is_pin0(&self) -> bool {
108        *self == Muxposselect::Pin0
109    }
110    #[doc = "ADC AIN1 Pin"]
111    #[inline(always)]
112    pub fn is_pin1(&self) -> bool {
113        *self == Muxposselect::Pin1
114    }
115    #[doc = "ADC AIN2 Pin"]
116    #[inline(always)]
117    pub fn is_pin2(&self) -> bool {
118        *self == Muxposselect::Pin2
119    }
120    #[doc = "ADC AIN3 Pin"]
121    #[inline(always)]
122    pub fn is_pin3(&self) -> bool {
123        *self == Muxposselect::Pin3
124    }
125    #[doc = "ADC AIN4 Pin"]
126    #[inline(always)]
127    pub fn is_pin4(&self) -> bool {
128        *self == Muxposselect::Pin4
129    }
130    #[doc = "ADC AIN5 Pin"]
131    #[inline(always)]
132    pub fn is_pin5(&self) -> bool {
133        *self == Muxposselect::Pin5
134    }
135    #[doc = "ADC AIN6 Pin"]
136    #[inline(always)]
137    pub fn is_pin6(&self) -> bool {
138        *self == Muxposselect::Pin6
139    }
140    #[doc = "ADC AIN7 Pin"]
141    #[inline(always)]
142    pub fn is_pin7(&self) -> bool {
143        *self == Muxposselect::Pin7
144    }
145    #[doc = "ADC AIN8 Pin"]
146    #[inline(always)]
147    pub fn is_pin8(&self) -> bool {
148        *self == Muxposselect::Pin8
149    }
150    #[doc = "ADC AIN9 Pin"]
151    #[inline(always)]
152    pub fn is_pin9(&self) -> bool {
153        *self == Muxposselect::Pin9
154    }
155    #[doc = "ADC AIN10 Pin"]
156    #[inline(always)]
157    pub fn is_pin10(&self) -> bool {
158        *self == Muxposselect::Pin10
159    }
160    #[doc = "ADC AIN11 Pin"]
161    #[inline(always)]
162    pub fn is_pin11(&self) -> bool {
163        *self == Muxposselect::Pin11
164    }
165    #[doc = "ADC AIN12 Pin"]
166    #[inline(always)]
167    pub fn is_pin12(&self) -> bool {
168        *self == Muxposselect::Pin12
169    }
170    #[doc = "ADC AIN13 Pin"]
171    #[inline(always)]
172    pub fn is_pin13(&self) -> bool {
173        *self == Muxposselect::Pin13
174    }
175    #[doc = "ADC AIN14 Pin"]
176    #[inline(always)]
177    pub fn is_pin14(&self) -> bool {
178        *self == Muxposselect::Pin14
179    }
180    #[doc = "ADC AIN15 Pin"]
181    #[inline(always)]
182    pub fn is_pin15(&self) -> bool {
183        *self == Muxposselect::Pin15
184    }
185    #[doc = "ADC AIN16 Pin"]
186    #[inline(always)]
187    pub fn is_pin16(&self) -> bool {
188        *self == Muxposselect::Pin16
189    }
190    #[doc = "ADC AIN17 Pin"]
191    #[inline(always)]
192    pub fn is_pin17(&self) -> bool {
193        *self == Muxposselect::Pin17
194    }
195    #[doc = "ADC AIN18 Pin"]
196    #[inline(always)]
197    pub fn is_pin18(&self) -> bool {
198        *self == Muxposselect::Pin18
199    }
200    #[doc = "ADC AIN19 Pin"]
201    #[inline(always)]
202    pub fn is_pin19(&self) -> bool {
203        *self == Muxposselect::Pin19
204    }
205    #[doc = "Temperature Reference"]
206    #[inline(always)]
207    pub fn is_temp(&self) -> bool {
208        *self == Muxposselect::Temp
209    }
210    #[doc = "Bandgap Voltage"]
211    #[inline(always)]
212    pub fn is_bandgap(&self) -> bool {
213        *self == Muxposselect::Bandgap
214    }
215    #[doc = "1/4 Scaled Core Supply"]
216    #[inline(always)]
217    pub fn is_scaledcorevcc(&self) -> bool {
218        *self == Muxposselect::Scaledcorevcc
219    }
220    #[doc = "1/4 Scaled I/O Supply"]
221    #[inline(always)]
222    pub fn is_scalediovcc(&self) -> bool {
223        *self == Muxposselect::Scalediovcc
224    }
225    #[doc = "DAC Output"]
226    #[inline(always)]
227    pub fn is_dac(&self) -> bool {
228        *self == Muxposselect::Dac
229    }
230}
231#[doc = "Field `MUXPOS` writer - Positive Mux Input Selection"]
232pub type MuxposW<'a, REG> = crate::FieldWriter<'a, REG, 5, Muxposselect>;
233impl<'a, REG> MuxposW<'a, REG>
234where
235    REG: crate::Writable + crate::RegisterSpec,
236    REG::Ux: From<u8>,
237{
238    #[doc = "ADC AIN0 Pin"]
239    #[inline(always)]
240    pub fn pin0(self) -> &'a mut crate::W<REG> {
241        self.variant(Muxposselect::Pin0)
242    }
243    #[doc = "ADC AIN1 Pin"]
244    #[inline(always)]
245    pub fn pin1(self) -> &'a mut crate::W<REG> {
246        self.variant(Muxposselect::Pin1)
247    }
248    #[doc = "ADC AIN2 Pin"]
249    #[inline(always)]
250    pub fn pin2(self) -> &'a mut crate::W<REG> {
251        self.variant(Muxposselect::Pin2)
252    }
253    #[doc = "ADC AIN3 Pin"]
254    #[inline(always)]
255    pub fn pin3(self) -> &'a mut crate::W<REG> {
256        self.variant(Muxposselect::Pin3)
257    }
258    #[doc = "ADC AIN4 Pin"]
259    #[inline(always)]
260    pub fn pin4(self) -> &'a mut crate::W<REG> {
261        self.variant(Muxposselect::Pin4)
262    }
263    #[doc = "ADC AIN5 Pin"]
264    #[inline(always)]
265    pub fn pin5(self) -> &'a mut crate::W<REG> {
266        self.variant(Muxposselect::Pin5)
267    }
268    #[doc = "ADC AIN6 Pin"]
269    #[inline(always)]
270    pub fn pin6(self) -> &'a mut crate::W<REG> {
271        self.variant(Muxposselect::Pin6)
272    }
273    #[doc = "ADC AIN7 Pin"]
274    #[inline(always)]
275    pub fn pin7(self) -> &'a mut crate::W<REG> {
276        self.variant(Muxposselect::Pin7)
277    }
278    #[doc = "ADC AIN8 Pin"]
279    #[inline(always)]
280    pub fn pin8(self) -> &'a mut crate::W<REG> {
281        self.variant(Muxposselect::Pin8)
282    }
283    #[doc = "ADC AIN9 Pin"]
284    #[inline(always)]
285    pub fn pin9(self) -> &'a mut crate::W<REG> {
286        self.variant(Muxposselect::Pin9)
287    }
288    #[doc = "ADC AIN10 Pin"]
289    #[inline(always)]
290    pub fn pin10(self) -> &'a mut crate::W<REG> {
291        self.variant(Muxposselect::Pin10)
292    }
293    #[doc = "ADC AIN11 Pin"]
294    #[inline(always)]
295    pub fn pin11(self) -> &'a mut crate::W<REG> {
296        self.variant(Muxposselect::Pin11)
297    }
298    #[doc = "ADC AIN12 Pin"]
299    #[inline(always)]
300    pub fn pin12(self) -> &'a mut crate::W<REG> {
301        self.variant(Muxposselect::Pin12)
302    }
303    #[doc = "ADC AIN13 Pin"]
304    #[inline(always)]
305    pub fn pin13(self) -> &'a mut crate::W<REG> {
306        self.variant(Muxposselect::Pin13)
307    }
308    #[doc = "ADC AIN14 Pin"]
309    #[inline(always)]
310    pub fn pin14(self) -> &'a mut crate::W<REG> {
311        self.variant(Muxposselect::Pin14)
312    }
313    #[doc = "ADC AIN15 Pin"]
314    #[inline(always)]
315    pub fn pin15(self) -> &'a mut crate::W<REG> {
316        self.variant(Muxposselect::Pin15)
317    }
318    #[doc = "ADC AIN16 Pin"]
319    #[inline(always)]
320    pub fn pin16(self) -> &'a mut crate::W<REG> {
321        self.variant(Muxposselect::Pin16)
322    }
323    #[doc = "ADC AIN17 Pin"]
324    #[inline(always)]
325    pub fn pin17(self) -> &'a mut crate::W<REG> {
326        self.variant(Muxposselect::Pin17)
327    }
328    #[doc = "ADC AIN18 Pin"]
329    #[inline(always)]
330    pub fn pin18(self) -> &'a mut crate::W<REG> {
331        self.variant(Muxposselect::Pin18)
332    }
333    #[doc = "ADC AIN19 Pin"]
334    #[inline(always)]
335    pub fn pin19(self) -> &'a mut crate::W<REG> {
336        self.variant(Muxposselect::Pin19)
337    }
338    #[doc = "Temperature Reference"]
339    #[inline(always)]
340    pub fn temp(self) -> &'a mut crate::W<REG> {
341        self.variant(Muxposselect::Temp)
342    }
343    #[doc = "Bandgap Voltage"]
344    #[inline(always)]
345    pub fn bandgap(self) -> &'a mut crate::W<REG> {
346        self.variant(Muxposselect::Bandgap)
347    }
348    #[doc = "1/4 Scaled Core Supply"]
349    #[inline(always)]
350    pub fn scaledcorevcc(self) -> &'a mut crate::W<REG> {
351        self.variant(Muxposselect::Scaledcorevcc)
352    }
353    #[doc = "1/4 Scaled I/O Supply"]
354    #[inline(always)]
355    pub fn scalediovcc(self) -> &'a mut crate::W<REG> {
356        self.variant(Muxposselect::Scalediovcc)
357    }
358    #[doc = "DAC Output"]
359    #[inline(always)]
360    pub fn dac(self) -> &'a mut crate::W<REG> {
361        self.variant(Muxposselect::Dac)
362    }
363}
364#[doc = "Negative Mux Input Selection\n\nValue on reset: 0"]
365#[derive(Clone, Copy, Debug, PartialEq, Eq)]
366#[repr(u8)]
367pub enum Muxnegselect {
368    #[doc = "0: ADC AIN0 Pin"]
369    Pin0 = 0,
370    #[doc = "1: ADC AIN1 Pin"]
371    Pin1 = 1,
372    #[doc = "2: ADC AIN2 Pin"]
373    Pin2 = 2,
374    #[doc = "3: ADC AIN3 Pin"]
375    Pin3 = 3,
376    #[doc = "4: ADC AIN4 Pin"]
377    Pin4 = 4,
378    #[doc = "5: ADC AIN5 Pin"]
379    Pin5 = 5,
380    #[doc = "6: ADC AIN6 Pin"]
381    Pin6 = 6,
382    #[doc = "7: ADC AIN7 Pin"]
383    Pin7 = 7,
384    #[doc = "24: Internal Ground"]
385    Gnd = 24,
386    #[doc = "25: I/O Ground"]
387    Iognd = 25,
388}
389impl From<Muxnegselect> for u8 {
390    #[inline(always)]
391    fn from(variant: Muxnegselect) -> Self {
392        variant as _
393    }
394}
395impl crate::FieldSpec for Muxnegselect {
396    type Ux = u8;
397}
398impl crate::IsEnum for Muxnegselect {}
399#[doc = "Field `MUXNEG` reader - Negative Mux Input Selection"]
400pub type MuxnegR = crate::FieldReader<Muxnegselect>;
401impl MuxnegR {
402    #[doc = "Get enumerated values variant"]
403    #[inline(always)]
404    pub const fn variant(&self) -> Option<Muxnegselect> {
405        match self.bits {
406            0 => Some(Muxnegselect::Pin0),
407            1 => Some(Muxnegselect::Pin1),
408            2 => Some(Muxnegselect::Pin2),
409            3 => Some(Muxnegselect::Pin3),
410            4 => Some(Muxnegselect::Pin4),
411            5 => Some(Muxnegselect::Pin5),
412            6 => Some(Muxnegselect::Pin6),
413            7 => Some(Muxnegselect::Pin7),
414            24 => Some(Muxnegselect::Gnd),
415            25 => Some(Muxnegselect::Iognd),
416            _ => None,
417        }
418    }
419    #[doc = "ADC AIN0 Pin"]
420    #[inline(always)]
421    pub fn is_pin0(&self) -> bool {
422        *self == Muxnegselect::Pin0
423    }
424    #[doc = "ADC AIN1 Pin"]
425    #[inline(always)]
426    pub fn is_pin1(&self) -> bool {
427        *self == Muxnegselect::Pin1
428    }
429    #[doc = "ADC AIN2 Pin"]
430    #[inline(always)]
431    pub fn is_pin2(&self) -> bool {
432        *self == Muxnegselect::Pin2
433    }
434    #[doc = "ADC AIN3 Pin"]
435    #[inline(always)]
436    pub fn is_pin3(&self) -> bool {
437        *self == Muxnegselect::Pin3
438    }
439    #[doc = "ADC AIN4 Pin"]
440    #[inline(always)]
441    pub fn is_pin4(&self) -> bool {
442        *self == Muxnegselect::Pin4
443    }
444    #[doc = "ADC AIN5 Pin"]
445    #[inline(always)]
446    pub fn is_pin5(&self) -> bool {
447        *self == Muxnegselect::Pin5
448    }
449    #[doc = "ADC AIN6 Pin"]
450    #[inline(always)]
451    pub fn is_pin6(&self) -> bool {
452        *self == Muxnegselect::Pin6
453    }
454    #[doc = "ADC AIN7 Pin"]
455    #[inline(always)]
456    pub fn is_pin7(&self) -> bool {
457        *self == Muxnegselect::Pin7
458    }
459    #[doc = "Internal Ground"]
460    #[inline(always)]
461    pub fn is_gnd(&self) -> bool {
462        *self == Muxnegselect::Gnd
463    }
464    #[doc = "I/O Ground"]
465    #[inline(always)]
466    pub fn is_iognd(&self) -> bool {
467        *self == Muxnegselect::Iognd
468    }
469}
470#[doc = "Field `MUXNEG` writer - Negative Mux Input Selection"]
471pub type MuxnegW<'a, REG> = crate::FieldWriter<'a, REG, 5, Muxnegselect>;
472impl<'a, REG> MuxnegW<'a, REG>
473where
474    REG: crate::Writable + crate::RegisterSpec,
475    REG::Ux: From<u8>,
476{
477    #[doc = "ADC AIN0 Pin"]
478    #[inline(always)]
479    pub fn pin0(self) -> &'a mut crate::W<REG> {
480        self.variant(Muxnegselect::Pin0)
481    }
482    #[doc = "ADC AIN1 Pin"]
483    #[inline(always)]
484    pub fn pin1(self) -> &'a mut crate::W<REG> {
485        self.variant(Muxnegselect::Pin1)
486    }
487    #[doc = "ADC AIN2 Pin"]
488    #[inline(always)]
489    pub fn pin2(self) -> &'a mut crate::W<REG> {
490        self.variant(Muxnegselect::Pin2)
491    }
492    #[doc = "ADC AIN3 Pin"]
493    #[inline(always)]
494    pub fn pin3(self) -> &'a mut crate::W<REG> {
495        self.variant(Muxnegselect::Pin3)
496    }
497    #[doc = "ADC AIN4 Pin"]
498    #[inline(always)]
499    pub fn pin4(self) -> &'a mut crate::W<REG> {
500        self.variant(Muxnegselect::Pin4)
501    }
502    #[doc = "ADC AIN5 Pin"]
503    #[inline(always)]
504    pub fn pin5(self) -> &'a mut crate::W<REG> {
505        self.variant(Muxnegselect::Pin5)
506    }
507    #[doc = "ADC AIN6 Pin"]
508    #[inline(always)]
509    pub fn pin6(self) -> &'a mut crate::W<REG> {
510        self.variant(Muxnegselect::Pin6)
511    }
512    #[doc = "ADC AIN7 Pin"]
513    #[inline(always)]
514    pub fn pin7(self) -> &'a mut crate::W<REG> {
515        self.variant(Muxnegselect::Pin7)
516    }
517    #[doc = "Internal Ground"]
518    #[inline(always)]
519    pub fn gnd(self) -> &'a mut crate::W<REG> {
520        self.variant(Muxnegselect::Gnd)
521    }
522    #[doc = "I/O Ground"]
523    #[inline(always)]
524    pub fn iognd(self) -> &'a mut crate::W<REG> {
525        self.variant(Muxnegselect::Iognd)
526    }
527}
528#[doc = "Field `INPUTSCAN` reader - Number of Input Channels Included in Scan"]
529pub type InputscanR = crate::FieldReader;
530#[doc = "Field `INPUTSCAN` writer - Number of Input Channels Included in Scan"]
531pub type InputscanW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
532#[doc = "Field `INPUTOFFSET` reader - Positive Mux Setting Offset"]
533pub type InputoffsetR = crate::FieldReader;
534#[doc = "Field `INPUTOFFSET` writer - Positive Mux Setting Offset"]
535pub type InputoffsetW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
536#[doc = "Gain Factor Selection\n\nValue on reset: 0"]
537#[derive(Clone, Copy, Debug, PartialEq, Eq)]
538#[repr(u8)]
539pub enum Gainselect {
540    #[doc = "0: 1x"]
541    _1x = 0,
542    #[doc = "1: 2x"]
543    _2x = 1,
544    #[doc = "2: 4x"]
545    _4x = 2,
546    #[doc = "3: 8x"]
547    _8x = 3,
548    #[doc = "4: 16x"]
549    _16x = 4,
550    #[doc = "15: 1/2x"]
551    Div2 = 15,
552}
553impl From<Gainselect> for u8 {
554    #[inline(always)]
555    fn from(variant: Gainselect) -> Self {
556        variant as _
557    }
558}
559impl crate::FieldSpec for Gainselect {
560    type Ux = u8;
561}
562impl crate::IsEnum for Gainselect {}
563#[doc = "Field `GAIN` reader - Gain Factor Selection"]
564pub type GainR = crate::FieldReader<Gainselect>;
565impl GainR {
566    #[doc = "Get enumerated values variant"]
567    #[inline(always)]
568    pub const fn variant(&self) -> Option<Gainselect> {
569        match self.bits {
570            0 => Some(Gainselect::_1x),
571            1 => Some(Gainselect::_2x),
572            2 => Some(Gainselect::_4x),
573            3 => Some(Gainselect::_8x),
574            4 => Some(Gainselect::_16x),
575            15 => Some(Gainselect::Div2),
576            _ => None,
577        }
578    }
579    #[doc = "1x"]
580    #[inline(always)]
581    pub fn is_1x(&self) -> bool {
582        *self == Gainselect::_1x
583    }
584    #[doc = "2x"]
585    #[inline(always)]
586    pub fn is_2x(&self) -> bool {
587        *self == Gainselect::_2x
588    }
589    #[doc = "4x"]
590    #[inline(always)]
591    pub fn is_4x(&self) -> bool {
592        *self == Gainselect::_4x
593    }
594    #[doc = "8x"]
595    #[inline(always)]
596    pub fn is_8x(&self) -> bool {
597        *self == Gainselect::_8x
598    }
599    #[doc = "16x"]
600    #[inline(always)]
601    pub fn is_16x(&self) -> bool {
602        *self == Gainselect::_16x
603    }
604    #[doc = "1/2x"]
605    #[inline(always)]
606    pub fn is_div2(&self) -> bool {
607        *self == Gainselect::Div2
608    }
609}
610#[doc = "Field `GAIN` writer - Gain Factor Selection"]
611pub type GainW<'a, REG> = crate::FieldWriter<'a, REG, 4, Gainselect>;
612impl<'a, REG> GainW<'a, REG>
613where
614    REG: crate::Writable + crate::RegisterSpec,
615    REG::Ux: From<u8>,
616{
617    #[doc = "1x"]
618    #[inline(always)]
619    pub fn _1x(self) -> &'a mut crate::W<REG> {
620        self.variant(Gainselect::_1x)
621    }
622    #[doc = "2x"]
623    #[inline(always)]
624    pub fn _2x(self) -> &'a mut crate::W<REG> {
625        self.variant(Gainselect::_2x)
626    }
627    #[doc = "4x"]
628    #[inline(always)]
629    pub fn _4x(self) -> &'a mut crate::W<REG> {
630        self.variant(Gainselect::_4x)
631    }
632    #[doc = "8x"]
633    #[inline(always)]
634    pub fn _8x(self) -> &'a mut crate::W<REG> {
635        self.variant(Gainselect::_8x)
636    }
637    #[doc = "16x"]
638    #[inline(always)]
639    pub fn _16x(self) -> &'a mut crate::W<REG> {
640        self.variant(Gainselect::_16x)
641    }
642    #[doc = "1/2x"]
643    #[inline(always)]
644    pub fn div2(self) -> &'a mut crate::W<REG> {
645        self.variant(Gainselect::Div2)
646    }
647}
648impl R {
649    #[doc = "Bits 0:4 - Positive Mux Input Selection"]
650    #[inline(always)]
651    pub fn muxpos(&self) -> MuxposR {
652        MuxposR::new((self.bits & 0x1f) as u8)
653    }
654    #[doc = "Bits 8:12 - Negative Mux Input Selection"]
655    #[inline(always)]
656    pub fn muxneg(&self) -> MuxnegR {
657        MuxnegR::new(((self.bits >> 8) & 0x1f) as u8)
658    }
659    #[doc = "Bits 16:19 - Number of Input Channels Included in Scan"]
660    #[inline(always)]
661    pub fn inputscan(&self) -> InputscanR {
662        InputscanR::new(((self.bits >> 16) & 0x0f) as u8)
663    }
664    #[doc = "Bits 20:23 - Positive Mux Setting Offset"]
665    #[inline(always)]
666    pub fn inputoffset(&self) -> InputoffsetR {
667        InputoffsetR::new(((self.bits >> 20) & 0x0f) as u8)
668    }
669    #[doc = "Bits 24:27 - Gain Factor Selection"]
670    #[inline(always)]
671    pub fn gain(&self) -> GainR {
672        GainR::new(((self.bits >> 24) & 0x0f) as u8)
673    }
674}
675impl W {
676    #[doc = "Bits 0:4 - Positive Mux Input Selection"]
677    #[inline(always)]
678    #[must_use]
679    pub fn muxpos(&mut self) -> MuxposW<InputctrlSpec> {
680        MuxposW::new(self, 0)
681    }
682    #[doc = "Bits 8:12 - Negative Mux Input Selection"]
683    #[inline(always)]
684    #[must_use]
685    pub fn muxneg(&mut self) -> MuxnegW<InputctrlSpec> {
686        MuxnegW::new(self, 8)
687    }
688    #[doc = "Bits 16:19 - Number of Input Channels Included in Scan"]
689    #[inline(always)]
690    #[must_use]
691    pub fn inputscan(&mut self) -> InputscanW<InputctrlSpec> {
692        InputscanW::new(self, 16)
693    }
694    #[doc = "Bits 20:23 - Positive Mux Setting Offset"]
695    #[inline(always)]
696    #[must_use]
697    pub fn inputoffset(&mut self) -> InputoffsetW<InputctrlSpec> {
698        InputoffsetW::new(self, 20)
699    }
700    #[doc = "Bits 24:27 - Gain Factor Selection"]
701    #[inline(always)]
702    #[must_use]
703    pub fn gain(&mut self) -> GainW<InputctrlSpec> {
704        GainW::new(self, 24)
705    }
706}
707#[doc = "Input Control\n\nYou can [`read`](crate::Reg::read) this register and get [`inputctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`inputctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
708pub struct InputctrlSpec;
709impl crate::RegisterSpec for InputctrlSpec {
710    type Ux = u32;
711}
712#[doc = "`read()` method returns [`inputctrl::R`](R) reader structure"]
713impl crate::Readable for InputctrlSpec {}
714#[doc = "`write(|w| ..)` method takes [`inputctrl::W`](W) writer structure"]
715impl crate::Writable for InputctrlSpec {
716    type Safety = crate::Unsafe;
717    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
718    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
719}
720#[doc = "`reset()` method sets INPUTCTRL to value 0"]
721impl crate::Resettable for InputctrlSpec {
722    const RESET_VALUE: u32 = 0;
723}
atsamd21g/adc/inputctrl.rs

atsamd21g/adc/
inputctrl.rs
