atsamd21g/tcc0/
wave.rs

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1#[doc = "Register `WAVE` reader"]
2pub type R = crate::R<WaveSpec>;
3#[doc = "Register `WAVE` writer"]
4pub type W = crate::W<WaveSpec>;
5#[doc = "Waveform Generation\n\nValue on reset: 0"]
6#[derive(Clone, Copy, Debug, PartialEq, Eq)]
7#[repr(u8)]
8pub enum Wavegenselect {
9    #[doc = "0: Normal frequency"]
10    Nfrq = 0,
11    #[doc = "1: Match frequency"]
12    Mfrq = 1,
13    #[doc = "2: Normal PWM"]
14    Npwm = 2,
15    #[doc = "4: Dual-slope critical"]
16    Dscritical = 4,
17    #[doc = "5: Dual-slope with interrupt/event condition when COUNT reaches ZERO"]
18    Dsbottom = 5,
19    #[doc = "6: Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP"]
20    Dsboth = 6,
21    #[doc = "7: Dual-slope with interrupt/event condition when COUNT reaches TOP"]
22    Dstop = 7,
23}
24impl From<Wavegenselect> for u8 {
25    #[inline(always)]
26    fn from(variant: Wavegenselect) -> Self {
27        variant as _
28    }
29}
30impl crate::FieldSpec for Wavegenselect {
31    type Ux = u8;
32}
33impl crate::IsEnum for Wavegenselect {}
34#[doc = "Field `WAVEGEN` reader - Waveform Generation"]
35pub type WavegenR = crate::FieldReader<Wavegenselect>;
36impl WavegenR {
37    #[doc = "Get enumerated values variant"]
38    #[inline(always)]
39    pub const fn variant(&self) -> Option<Wavegenselect> {
40        match self.bits {
41            0 => Some(Wavegenselect::Nfrq),
42            1 => Some(Wavegenselect::Mfrq),
43            2 => Some(Wavegenselect::Npwm),
44            4 => Some(Wavegenselect::Dscritical),
45            5 => Some(Wavegenselect::Dsbottom),
46            6 => Some(Wavegenselect::Dsboth),
47            7 => Some(Wavegenselect::Dstop),
48            _ => None,
49        }
50    }
51    #[doc = "Normal frequency"]
52    #[inline(always)]
53    pub fn is_nfrq(&self) -> bool {
54        *self == Wavegenselect::Nfrq
55    }
56    #[doc = "Match frequency"]
57    #[inline(always)]
58    pub fn is_mfrq(&self) -> bool {
59        *self == Wavegenselect::Mfrq
60    }
61    #[doc = "Normal PWM"]
62    #[inline(always)]
63    pub fn is_npwm(&self) -> bool {
64        *self == Wavegenselect::Npwm
65    }
66    #[doc = "Dual-slope critical"]
67    #[inline(always)]
68    pub fn is_dscritical(&self) -> bool {
69        *self == Wavegenselect::Dscritical
70    }
71    #[doc = "Dual-slope with interrupt/event condition when COUNT reaches ZERO"]
72    #[inline(always)]
73    pub fn is_dsbottom(&self) -> bool {
74        *self == Wavegenselect::Dsbottom
75    }
76    #[doc = "Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP"]
77    #[inline(always)]
78    pub fn is_dsboth(&self) -> bool {
79        *self == Wavegenselect::Dsboth
80    }
81    #[doc = "Dual-slope with interrupt/event condition when COUNT reaches TOP"]
82    #[inline(always)]
83    pub fn is_dstop(&self) -> bool {
84        *self == Wavegenselect::Dstop
85    }
86}
87#[doc = "Field `WAVEGEN` writer - Waveform Generation"]
88pub type WavegenW<'a, REG> = crate::FieldWriter<'a, REG, 3, Wavegenselect>;
89impl<'a, REG> WavegenW<'a, REG>
90where
91    REG: crate::Writable + crate::RegisterSpec,
92    REG::Ux: From<u8>,
93{
94    #[doc = "Normal frequency"]
95    #[inline(always)]
96    pub fn nfrq(self) -> &'a mut crate::W<REG> {
97        self.variant(Wavegenselect::Nfrq)
98    }
99    #[doc = "Match frequency"]
100    #[inline(always)]
101    pub fn mfrq(self) -> &'a mut crate::W<REG> {
102        self.variant(Wavegenselect::Mfrq)
103    }
104    #[doc = "Normal PWM"]
105    #[inline(always)]
106    pub fn npwm(self) -> &'a mut crate::W<REG> {
107        self.variant(Wavegenselect::Npwm)
108    }
109    #[doc = "Dual-slope critical"]
110    #[inline(always)]
111    pub fn dscritical(self) -> &'a mut crate::W<REG> {
112        self.variant(Wavegenselect::Dscritical)
113    }
114    #[doc = "Dual-slope with interrupt/event condition when COUNT reaches ZERO"]
115    #[inline(always)]
116    pub fn dsbottom(self) -> &'a mut crate::W<REG> {
117        self.variant(Wavegenselect::Dsbottom)
118    }
119    #[doc = "Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP"]
120    #[inline(always)]
121    pub fn dsboth(self) -> &'a mut crate::W<REG> {
122        self.variant(Wavegenselect::Dsboth)
123    }
124    #[doc = "Dual-slope with interrupt/event condition when COUNT reaches TOP"]
125    #[inline(always)]
126    pub fn dstop(self) -> &'a mut crate::W<REG> {
127        self.variant(Wavegenselect::Dstop)
128    }
129}
130#[doc = "Ramp Mode\n\nValue on reset: 0"]
131#[derive(Clone, Copy, Debug, PartialEq, Eq)]
132#[repr(u8)]
133pub enum Rampselect {
134    #[doc = "0: RAMP1 operation"]
135    Ramp1 = 0,
136    #[doc = "1: Alternative RAMP2 operation"]
137    Ramp2a = 1,
138    #[doc = "2: RAMP2 operation"]
139    Ramp2 = 2,
140}
141impl From<Rampselect> for u8 {
142    #[inline(always)]
143    fn from(variant: Rampselect) -> Self {
144        variant as _
145    }
146}
147impl crate::FieldSpec for Rampselect {
148    type Ux = u8;
149}
150impl crate::IsEnum for Rampselect {}
151#[doc = "Field `RAMP` reader - Ramp Mode"]
152pub type RampR = crate::FieldReader<Rampselect>;
153impl RampR {
154    #[doc = "Get enumerated values variant"]
155    #[inline(always)]
156    pub const fn variant(&self) -> Option<Rampselect> {
157        match self.bits {
158            0 => Some(Rampselect::Ramp1),
159            1 => Some(Rampselect::Ramp2a),
160            2 => Some(Rampselect::Ramp2),
161            _ => None,
162        }
163    }
164    #[doc = "RAMP1 operation"]
165    #[inline(always)]
166    pub fn is_ramp1(&self) -> bool {
167        *self == Rampselect::Ramp1
168    }
169    #[doc = "Alternative RAMP2 operation"]
170    #[inline(always)]
171    pub fn is_ramp2a(&self) -> bool {
172        *self == Rampselect::Ramp2a
173    }
174    #[doc = "RAMP2 operation"]
175    #[inline(always)]
176    pub fn is_ramp2(&self) -> bool {
177        *self == Rampselect::Ramp2
178    }
179}
180#[doc = "Field `RAMP` writer - Ramp Mode"]
181pub type RampW<'a, REG> = crate::FieldWriter<'a, REG, 2, Rampselect>;
182impl<'a, REG> RampW<'a, REG>
183where
184    REG: crate::Writable + crate::RegisterSpec,
185    REG::Ux: From<u8>,
186{
187    #[doc = "RAMP1 operation"]
188    #[inline(always)]
189    pub fn ramp1(self) -> &'a mut crate::W<REG> {
190        self.variant(Rampselect::Ramp1)
191    }
192    #[doc = "Alternative RAMP2 operation"]
193    #[inline(always)]
194    pub fn ramp2a(self) -> &'a mut crate::W<REG> {
195        self.variant(Rampselect::Ramp2a)
196    }
197    #[doc = "RAMP2 operation"]
198    #[inline(always)]
199    pub fn ramp2(self) -> &'a mut crate::W<REG> {
200        self.variant(Rampselect::Ramp2)
201    }
202}
203#[doc = "Field `CIPEREN` reader - Circular period Enable"]
204pub type CiperenR = crate::BitReader;
205#[doc = "Field `CIPEREN` writer - Circular period Enable"]
206pub type CiperenW<'a, REG> = crate::BitWriter<'a, REG>;
207#[doc = "Field `CICCEN0` reader - Circular Channel 0 Enable"]
208pub type Ciccen0R = crate::BitReader;
209#[doc = "Field `CICCEN0` writer - Circular Channel 0 Enable"]
210pub type Ciccen0W<'a, REG> = crate::BitWriter<'a, REG>;
211#[doc = "Field `CICCEN1` reader - Circular Channel 1 Enable"]
212pub type Ciccen1R = crate::BitReader;
213#[doc = "Field `CICCEN1` writer - Circular Channel 1 Enable"]
214pub type Ciccen1W<'a, REG> = crate::BitWriter<'a, REG>;
215#[doc = "Field `CICCEN2` reader - Circular Channel 2 Enable"]
216pub type Ciccen2R = crate::BitReader;
217#[doc = "Field `CICCEN2` writer - Circular Channel 2 Enable"]
218pub type Ciccen2W<'a, REG> = crate::BitWriter<'a, REG>;
219#[doc = "Field `CICCEN3` reader - Circular Channel 3 Enable"]
220pub type Ciccen3R = crate::BitReader;
221#[doc = "Field `CICCEN3` writer - Circular Channel 3 Enable"]
222pub type Ciccen3W<'a, REG> = crate::BitWriter<'a, REG>;
223#[doc = "Field `POL0` reader - Channel 0 Polarity"]
224pub type Pol0R = crate::BitReader;
225#[doc = "Field `POL0` writer - Channel 0 Polarity"]
226pub type Pol0W<'a, REG> = crate::BitWriter<'a, REG>;
227#[doc = "Field `POL1` reader - Channel 1 Polarity"]
228pub type Pol1R = crate::BitReader;
229#[doc = "Field `POL1` writer - Channel 1 Polarity"]
230pub type Pol1W<'a, REG> = crate::BitWriter<'a, REG>;
231#[doc = "Field `POL2` reader - Channel 2 Polarity"]
232pub type Pol2R = crate::BitReader;
233#[doc = "Field `POL2` writer - Channel 2 Polarity"]
234pub type Pol2W<'a, REG> = crate::BitWriter<'a, REG>;
235#[doc = "Field `POL3` reader - Channel 3 Polarity"]
236pub type Pol3R = crate::BitReader;
237#[doc = "Field `POL3` writer - Channel 3 Polarity"]
238pub type Pol3W<'a, REG> = crate::BitWriter<'a, REG>;
239#[doc = "Field `SWAP0` reader - Swap DTI Output Pair 0"]
240pub type Swap0R = crate::BitReader;
241#[doc = "Field `SWAP0` writer - Swap DTI Output Pair 0"]
242pub type Swap0W<'a, REG> = crate::BitWriter<'a, REG>;
243#[doc = "Field `SWAP1` reader - Swap DTI Output Pair 1"]
244pub type Swap1R = crate::BitReader;
245#[doc = "Field `SWAP1` writer - Swap DTI Output Pair 1"]
246pub type Swap1W<'a, REG> = crate::BitWriter<'a, REG>;
247#[doc = "Field `SWAP2` reader - Swap DTI Output Pair 2"]
248pub type Swap2R = crate::BitReader;
249#[doc = "Field `SWAP2` writer - Swap DTI Output Pair 2"]
250pub type Swap2W<'a, REG> = crate::BitWriter<'a, REG>;
251#[doc = "Field `SWAP3` reader - Swap DTI Output Pair 3"]
252pub type Swap3R = crate::BitReader;
253#[doc = "Field `SWAP3` writer - Swap DTI Output Pair 3"]
254pub type Swap3W<'a, REG> = crate::BitWriter<'a, REG>;
255impl R {
256    #[doc = "Bits 0:2 - Waveform Generation"]
257    #[inline(always)]
258    pub fn wavegen(&self) -> WavegenR {
259        WavegenR::new((self.bits & 7) as u8)
260    }
261    #[doc = "Bits 4:5 - Ramp Mode"]
262    #[inline(always)]
263    pub fn ramp(&self) -> RampR {
264        RampR::new(((self.bits >> 4) & 3) as u8)
265    }
266    #[doc = "Bit 7 - Circular period Enable"]
267    #[inline(always)]
268    pub fn ciperen(&self) -> CiperenR {
269        CiperenR::new(((self.bits >> 7) & 1) != 0)
270    }
271    #[doc = "Bit 8 - Circular Channel 0 Enable"]
272    #[inline(always)]
273    pub fn ciccen0(&self) -> Ciccen0R {
274        Ciccen0R::new(((self.bits >> 8) & 1) != 0)
275    }
276    #[doc = "Bit 9 - Circular Channel 1 Enable"]
277    #[inline(always)]
278    pub fn ciccen1(&self) -> Ciccen1R {
279        Ciccen1R::new(((self.bits >> 9) & 1) != 0)
280    }
281    #[doc = "Bit 10 - Circular Channel 2 Enable"]
282    #[inline(always)]
283    pub fn ciccen2(&self) -> Ciccen2R {
284        Ciccen2R::new(((self.bits >> 10) & 1) != 0)
285    }
286    #[doc = "Bit 11 - Circular Channel 3 Enable"]
287    #[inline(always)]
288    pub fn ciccen3(&self) -> Ciccen3R {
289        Ciccen3R::new(((self.bits >> 11) & 1) != 0)
290    }
291    #[doc = "Bit 16 - Channel 0 Polarity"]
292    #[inline(always)]
293    pub fn pol0(&self) -> Pol0R {
294        Pol0R::new(((self.bits >> 16) & 1) != 0)
295    }
296    #[doc = "Bit 17 - Channel 1 Polarity"]
297    #[inline(always)]
298    pub fn pol1(&self) -> Pol1R {
299        Pol1R::new(((self.bits >> 17) & 1) != 0)
300    }
301    #[doc = "Bit 18 - Channel 2 Polarity"]
302    #[inline(always)]
303    pub fn pol2(&self) -> Pol2R {
304        Pol2R::new(((self.bits >> 18) & 1) != 0)
305    }
306    #[doc = "Bit 19 - Channel 3 Polarity"]
307    #[inline(always)]
308    pub fn pol3(&self) -> Pol3R {
309        Pol3R::new(((self.bits >> 19) & 1) != 0)
310    }
311    #[doc = "Bit 24 - Swap DTI Output Pair 0"]
312    #[inline(always)]
313    pub fn swap0(&self) -> Swap0R {
314        Swap0R::new(((self.bits >> 24) & 1) != 0)
315    }
316    #[doc = "Bit 25 - Swap DTI Output Pair 1"]
317    #[inline(always)]
318    pub fn swap1(&self) -> Swap1R {
319        Swap1R::new(((self.bits >> 25) & 1) != 0)
320    }
321    #[doc = "Bit 26 - Swap DTI Output Pair 2"]
322    #[inline(always)]
323    pub fn swap2(&self) -> Swap2R {
324        Swap2R::new(((self.bits >> 26) & 1) != 0)
325    }
326    #[doc = "Bit 27 - Swap DTI Output Pair 3"]
327    #[inline(always)]
328    pub fn swap3(&self) -> Swap3R {
329        Swap3R::new(((self.bits >> 27) & 1) != 0)
330    }
331}
332impl W {
333    #[doc = "Bits 0:2 - Waveform Generation"]
334    #[inline(always)]
335    #[must_use]
336    pub fn wavegen(&mut self) -> WavegenW<WaveSpec> {
337        WavegenW::new(self, 0)
338    }
339    #[doc = "Bits 4:5 - Ramp Mode"]
340    #[inline(always)]
341    #[must_use]
342    pub fn ramp(&mut self) -> RampW<WaveSpec> {
343        RampW::new(self, 4)
344    }
345    #[doc = "Bit 7 - Circular period Enable"]
346    #[inline(always)]
347    #[must_use]
348    pub fn ciperen(&mut self) -> CiperenW<WaveSpec> {
349        CiperenW::new(self, 7)
350    }
351    #[doc = "Bit 8 - Circular Channel 0 Enable"]
352    #[inline(always)]
353    #[must_use]
354    pub fn ciccen0(&mut self) -> Ciccen0W<WaveSpec> {
355        Ciccen0W::new(self, 8)
356    }
357    #[doc = "Bit 9 - Circular Channel 1 Enable"]
358    #[inline(always)]
359    #[must_use]
360    pub fn ciccen1(&mut self) -> Ciccen1W<WaveSpec> {
361        Ciccen1W::new(self, 9)
362    }
363    #[doc = "Bit 10 - Circular Channel 2 Enable"]
364    #[inline(always)]
365    #[must_use]
366    pub fn ciccen2(&mut self) -> Ciccen2W<WaveSpec> {
367        Ciccen2W::new(self, 10)
368    }
369    #[doc = "Bit 11 - Circular Channel 3 Enable"]
370    #[inline(always)]
371    #[must_use]
372    pub fn ciccen3(&mut self) -> Ciccen3W<WaveSpec> {
373        Ciccen3W::new(self, 11)
374    }
375    #[doc = "Bit 16 - Channel 0 Polarity"]
376    #[inline(always)]
377    #[must_use]
378    pub fn pol0(&mut self) -> Pol0W<WaveSpec> {
379        Pol0W::new(self, 16)
380    }
381    #[doc = "Bit 17 - Channel 1 Polarity"]
382    #[inline(always)]
383    #[must_use]
384    pub fn pol1(&mut self) -> Pol1W<WaveSpec> {
385        Pol1W::new(self, 17)
386    }
387    #[doc = "Bit 18 - Channel 2 Polarity"]
388    #[inline(always)]
389    #[must_use]
390    pub fn pol2(&mut self) -> Pol2W<WaveSpec> {
391        Pol2W::new(self, 18)
392    }
393    #[doc = "Bit 19 - Channel 3 Polarity"]
394    #[inline(always)]
395    #[must_use]
396    pub fn pol3(&mut self) -> Pol3W<WaveSpec> {
397        Pol3W::new(self, 19)
398    }
399    #[doc = "Bit 24 - Swap DTI Output Pair 0"]
400    #[inline(always)]
401    #[must_use]
402    pub fn swap0(&mut self) -> Swap0W<WaveSpec> {
403        Swap0W::new(self, 24)
404    }
405    #[doc = "Bit 25 - Swap DTI Output Pair 1"]
406    #[inline(always)]
407    #[must_use]
408    pub fn swap1(&mut self) -> Swap1W<WaveSpec> {
409        Swap1W::new(self, 25)
410    }
411    #[doc = "Bit 26 - Swap DTI Output Pair 2"]
412    #[inline(always)]
413    #[must_use]
414    pub fn swap2(&mut self) -> Swap2W<WaveSpec> {
415        Swap2W::new(self, 26)
416    }
417    #[doc = "Bit 27 - Swap DTI Output Pair 3"]
418    #[inline(always)]
419    #[must_use]
420    pub fn swap3(&mut self) -> Swap3W<WaveSpec> {
421        Swap3W::new(self, 27)
422    }
423}
424#[doc = "Waveform Control\n\nYou can [`read`](crate::Reg::read) this register and get [`wave::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wave::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
425pub struct WaveSpec;
426impl crate::RegisterSpec for WaveSpec {
427    type Ux = u32;
428}
429#[doc = "`read()` method returns [`wave::R`](R) reader structure"]
430impl crate::Readable for WaveSpec {}
431#[doc = "`write(|w| ..)` method takes [`wave::W`](W) writer structure"]
432impl crate::Writable for WaveSpec {
433    type Safety = crate::Unsafe;
434    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
435    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
436}
437#[doc = "`reset()` method sets WAVE to value 0"]
438impl crate::Resettable for WaveSpec {
439    const RESET_VALUE: u32 = 0;
440}
atsamd21g/tcc0/wave.rs

atsamd21g/tcc0/
wave.rs
