atsamd21g/gclk/
clkctrl.rs

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1#[doc = "Register `CLKCTRL` reader"]
2pub type R = crate::R<ClkctrlSpec>;
3#[doc = "Register `CLKCTRL` writer"]
4pub type W = crate::W<ClkctrlSpec>;
5#[doc = "Generic Clock Selection ID\n\nValue on reset: 0"]
6#[derive(Clone, Copy, Debug, PartialEq, Eq)]
7#[repr(u8)]
8pub enum Idselect {
9    #[doc = "0: DFLL48"]
10    Dfll48 = 0,
11    #[doc = "1: FDPLL"]
12    Fdpll = 1,
13    #[doc = "2: FDPLL32K"]
14    Fdpll32k = 2,
15    #[doc = "3: WDT"]
16    Wdt = 3,
17    #[doc = "4: RTC"]
18    Rtc = 4,
19    #[doc = "5: EIC"]
20    Eic = 5,
21    #[doc = "6: USB"]
22    Usb = 6,
23    #[doc = "7: EVSYS_0"]
24    Evsys0 = 7,
25    #[doc = "8: EVSYS_1"]
26    Evsys1 = 8,
27    #[doc = "9: EVSYS_2"]
28    Evsys2 = 9,
29    #[doc = "10: EVSYS_3"]
30    Evsys3 = 10,
31    #[doc = "11: EVSYS_4"]
32    Evsys4 = 11,
33    #[doc = "12: EVSYS_5"]
34    Evsys5 = 12,
35    #[doc = "13: EVSYS_6"]
36    Evsys6 = 13,
37    #[doc = "14: EVSYS_7"]
38    Evsys7 = 14,
39    #[doc = "15: EVSYS_8"]
40    Evsys8 = 15,
41    #[doc = "16: EVSYS_9"]
42    Evsys9 = 16,
43    #[doc = "17: EVSYS_10"]
44    Evsys10 = 17,
45    #[doc = "18: EVSYS_11"]
46    Evsys11 = 18,
47    #[doc = "19: SERCOMX_SLOW"]
48    SercomxSlow = 19,
49    #[doc = "20: SERCOM0_CORE"]
50    Sercom0Core = 20,
51    #[doc = "21: SERCOM1_CORE"]
52    Sercom1Core = 21,
53    #[doc = "22: SERCOM2_CORE"]
54    Sercom2Core = 22,
55    #[doc = "23: SERCOM3_CORE"]
56    Sercom3Core = 23,
57    #[doc = "24: SERCOM4_CORE"]
58    Sercom4Core = 24,
59    #[doc = "25: SERCOM5_CORE"]
60    Sercom5Core = 25,
61    #[doc = "26: TCC0_TCC1"]
62    Tcc0Tcc1 = 26,
63    #[doc = "27: TCC2_TC3"]
64    Tcc2Tc3 = 27,
65    #[doc = "28: TC4_TC5"]
66    Tc4Tc5 = 28,
67    #[doc = "29: TC6_TC7"]
68    Tc6Tc7 = 29,
69    #[doc = "30: ADC"]
70    Adc = 30,
71    #[doc = "31: AC_DIG"]
72    AcDig = 31,
73    #[doc = "32: AC_ANA"]
74    AcAna = 32,
75    #[doc = "33: DAC"]
76    Dac = 33,
77    #[doc = "35: I2S_0"]
78    I2s0 = 35,
79    #[doc = "36: I2S_1"]
80    I2s1 = 36,
81}
82impl From<Idselect> for u8 {
83    #[inline(always)]
84    fn from(variant: Idselect) -> Self {
85        variant as _
86    }
87}
88impl crate::FieldSpec for Idselect {
89    type Ux = u8;
90}
91impl crate::IsEnum for Idselect {}
92#[doc = "Field `ID` reader - Generic Clock Selection ID"]
93pub type IdR = crate::FieldReader<Idselect>;
94impl IdR {
95    #[doc = "Get enumerated values variant"]
96    #[inline(always)]
97    pub const fn variant(&self) -> Option<Idselect> {
98        match self.bits {
99            0 => Some(Idselect::Dfll48),
100            1 => Some(Idselect::Fdpll),
101            2 => Some(Idselect::Fdpll32k),
102            3 => Some(Idselect::Wdt),
103            4 => Some(Idselect::Rtc),
104            5 => Some(Idselect::Eic),
105            6 => Some(Idselect::Usb),
106            7 => Some(Idselect::Evsys0),
107            8 => Some(Idselect::Evsys1),
108            9 => Some(Idselect::Evsys2),
109            10 => Some(Idselect::Evsys3),
110            11 => Some(Idselect::Evsys4),
111            12 => Some(Idselect::Evsys5),
112            13 => Some(Idselect::Evsys6),
113            14 => Some(Idselect::Evsys7),
114            15 => Some(Idselect::Evsys8),
115            16 => Some(Idselect::Evsys9),
116            17 => Some(Idselect::Evsys10),
117            18 => Some(Idselect::Evsys11),
118            19 => Some(Idselect::SercomxSlow),
119            20 => Some(Idselect::Sercom0Core),
120            21 => Some(Idselect::Sercom1Core),
121            22 => Some(Idselect::Sercom2Core),
122            23 => Some(Idselect::Sercom3Core),
123            24 => Some(Idselect::Sercom4Core),
124            25 => Some(Idselect::Sercom5Core),
125            26 => Some(Idselect::Tcc0Tcc1),
126            27 => Some(Idselect::Tcc2Tc3),
127            28 => Some(Idselect::Tc4Tc5),
128            29 => Some(Idselect::Tc6Tc7),
129            30 => Some(Idselect::Adc),
130            31 => Some(Idselect::AcDig),
131            32 => Some(Idselect::AcAna),
132            33 => Some(Idselect::Dac),
133            35 => Some(Idselect::I2s0),
134            36 => Some(Idselect::I2s1),
135            _ => None,
136        }
137    }
138    #[doc = "DFLL48"]
139    #[inline(always)]
140    pub fn is_dfll48(&self) -> bool {
141        *self == Idselect::Dfll48
142    }
143    #[doc = "FDPLL"]
144    #[inline(always)]
145    pub fn is_fdpll(&self) -> bool {
146        *self == Idselect::Fdpll
147    }
148    #[doc = "FDPLL32K"]
149    #[inline(always)]
150    pub fn is_fdpll32k(&self) -> bool {
151        *self == Idselect::Fdpll32k
152    }
153    #[doc = "WDT"]
154    #[inline(always)]
155    pub fn is_wdt(&self) -> bool {
156        *self == Idselect::Wdt
157    }
158    #[doc = "RTC"]
159    #[inline(always)]
160    pub fn is_rtc(&self) -> bool {
161        *self == Idselect::Rtc
162    }
163    #[doc = "EIC"]
164    #[inline(always)]
165    pub fn is_eic(&self) -> bool {
166        *self == Idselect::Eic
167    }
168    #[doc = "USB"]
169    #[inline(always)]
170    pub fn is_usb(&self) -> bool {
171        *self == Idselect::Usb
172    }
173    #[doc = "EVSYS_0"]
174    #[inline(always)]
175    pub fn is_evsys_0(&self) -> bool {
176        *self == Idselect::Evsys0
177    }
178    #[doc = "EVSYS_1"]
179    #[inline(always)]
180    pub fn is_evsys_1(&self) -> bool {
181        *self == Idselect::Evsys1
182    }
183    #[doc = "EVSYS_2"]
184    #[inline(always)]
185    pub fn is_evsys_2(&self) -> bool {
186        *self == Idselect::Evsys2
187    }
188    #[doc = "EVSYS_3"]
189    #[inline(always)]
190    pub fn is_evsys_3(&self) -> bool {
191        *self == Idselect::Evsys3
192    }
193    #[doc = "EVSYS_4"]
194    #[inline(always)]
195    pub fn is_evsys_4(&self) -> bool {
196        *self == Idselect::Evsys4
197    }
198    #[doc = "EVSYS_5"]
199    #[inline(always)]
200    pub fn is_evsys_5(&self) -> bool {
201        *self == Idselect::Evsys5
202    }
203    #[doc = "EVSYS_6"]
204    #[inline(always)]
205    pub fn is_evsys_6(&self) -> bool {
206        *self == Idselect::Evsys6
207    }
208    #[doc = "EVSYS_7"]
209    #[inline(always)]
210    pub fn is_evsys_7(&self) -> bool {
211        *self == Idselect::Evsys7
212    }
213    #[doc = "EVSYS_8"]
214    #[inline(always)]
215    pub fn is_evsys_8(&self) -> bool {
216        *self == Idselect::Evsys8
217    }
218    #[doc = "EVSYS_9"]
219    #[inline(always)]
220    pub fn is_evsys_9(&self) -> bool {
221        *self == Idselect::Evsys9
222    }
223    #[doc = "EVSYS_10"]
224    #[inline(always)]
225    pub fn is_evsys_10(&self) -> bool {
226        *self == Idselect::Evsys10
227    }
228    #[doc = "EVSYS_11"]
229    #[inline(always)]
230    pub fn is_evsys_11(&self) -> bool {
231        *self == Idselect::Evsys11
232    }
233    #[doc = "SERCOMX_SLOW"]
234    #[inline(always)]
235    pub fn is_sercomx_slow(&self) -> bool {
236        *self == Idselect::SercomxSlow
237    }
238    #[doc = "SERCOM0_CORE"]
239    #[inline(always)]
240    pub fn is_sercom0_core(&self) -> bool {
241        *self == Idselect::Sercom0Core
242    }
243    #[doc = "SERCOM1_CORE"]
244    #[inline(always)]
245    pub fn is_sercom1_core(&self) -> bool {
246        *self == Idselect::Sercom1Core
247    }
248    #[doc = "SERCOM2_CORE"]
249    #[inline(always)]
250    pub fn is_sercom2_core(&self) -> bool {
251        *self == Idselect::Sercom2Core
252    }
253    #[doc = "SERCOM3_CORE"]
254    #[inline(always)]
255    pub fn is_sercom3_core(&self) -> bool {
256        *self == Idselect::Sercom3Core
257    }
258    #[doc = "SERCOM4_CORE"]
259    #[inline(always)]
260    pub fn is_sercom4_core(&self) -> bool {
261        *self == Idselect::Sercom4Core
262    }
263    #[doc = "SERCOM5_CORE"]
264    #[inline(always)]
265    pub fn is_sercom5_core(&self) -> bool {
266        *self == Idselect::Sercom5Core
267    }
268    #[doc = "TCC0_TCC1"]
269    #[inline(always)]
270    pub fn is_tcc0_tcc1(&self) -> bool {
271        *self == Idselect::Tcc0Tcc1
272    }
273    #[doc = "TCC2_TC3"]
274    #[inline(always)]
275    pub fn is_tcc2_tc3(&self) -> bool {
276        *self == Idselect::Tcc2Tc3
277    }
278    #[doc = "TC4_TC5"]
279    #[inline(always)]
280    pub fn is_tc4_tc5(&self) -> bool {
281        *self == Idselect::Tc4Tc5
282    }
283    #[doc = "TC6_TC7"]
284    #[inline(always)]
285    pub fn is_tc6_tc7(&self) -> bool {
286        *self == Idselect::Tc6Tc7
287    }
288    #[doc = "ADC"]
289    #[inline(always)]
290    pub fn is_adc(&self) -> bool {
291        *self == Idselect::Adc
292    }
293    #[doc = "AC_DIG"]
294    #[inline(always)]
295    pub fn is_ac_dig(&self) -> bool {
296        *self == Idselect::AcDig
297    }
298    #[doc = "AC_ANA"]
299    #[inline(always)]
300    pub fn is_ac_ana(&self) -> bool {
301        *self == Idselect::AcAna
302    }
303    #[doc = "DAC"]
304    #[inline(always)]
305    pub fn is_dac(&self) -> bool {
306        *self == Idselect::Dac
307    }
308    #[doc = "I2S_0"]
309    #[inline(always)]
310    pub fn is_i2s_0(&self) -> bool {
311        *self == Idselect::I2s0
312    }
313    #[doc = "I2S_1"]
314    #[inline(always)]
315    pub fn is_i2s_1(&self) -> bool {
316        *self == Idselect::I2s1
317    }
318}
319#[doc = "Field `ID` writer - Generic Clock Selection ID"]
320pub type IdW<'a, REG> = crate::FieldWriter<'a, REG, 6, Idselect>;
321impl<'a, REG> IdW<'a, REG>
322where
323    REG: crate::Writable + crate::RegisterSpec,
324    REG::Ux: From<u8>,
325{
326    #[doc = "DFLL48"]
327    #[inline(always)]
328    pub fn dfll48(self) -> &'a mut crate::W<REG> {
329        self.variant(Idselect::Dfll48)
330    }
331    #[doc = "FDPLL"]
332    #[inline(always)]
333    pub fn fdpll(self) -> &'a mut crate::W<REG> {
334        self.variant(Idselect::Fdpll)
335    }
336    #[doc = "FDPLL32K"]
337    #[inline(always)]
338    pub fn fdpll32k(self) -> &'a mut crate::W<REG> {
339        self.variant(Idselect::Fdpll32k)
340    }
341    #[doc = "WDT"]
342    #[inline(always)]
343    pub fn wdt(self) -> &'a mut crate::W<REG> {
344        self.variant(Idselect::Wdt)
345    }
346    #[doc = "RTC"]
347    #[inline(always)]
348    pub fn rtc(self) -> &'a mut crate::W<REG> {
349        self.variant(Idselect::Rtc)
350    }
351    #[doc = "EIC"]
352    #[inline(always)]
353    pub fn eic(self) -> &'a mut crate::W<REG> {
354        self.variant(Idselect::Eic)
355    }
356    #[doc = "USB"]
357    #[inline(always)]
358    pub fn usb(self) -> &'a mut crate::W<REG> {
359        self.variant(Idselect::Usb)
360    }
361    #[doc = "EVSYS_0"]
362    #[inline(always)]
363    pub fn evsys_0(self) -> &'a mut crate::W<REG> {
364        self.variant(Idselect::Evsys0)
365    }
366    #[doc = "EVSYS_1"]
367    #[inline(always)]
368    pub fn evsys_1(self) -> &'a mut crate::W<REG> {
369        self.variant(Idselect::Evsys1)
370    }
371    #[doc = "EVSYS_2"]
372    #[inline(always)]
373    pub fn evsys_2(self) -> &'a mut crate::W<REG> {
374        self.variant(Idselect::Evsys2)
375    }
376    #[doc = "EVSYS_3"]
377    #[inline(always)]
378    pub fn evsys_3(self) -> &'a mut crate::W<REG> {
379        self.variant(Idselect::Evsys3)
380    }
381    #[doc = "EVSYS_4"]
382    #[inline(always)]
383    pub fn evsys_4(self) -> &'a mut crate::W<REG> {
384        self.variant(Idselect::Evsys4)
385    }
386    #[doc = "EVSYS_5"]
387    #[inline(always)]
388    pub fn evsys_5(self) -> &'a mut crate::W<REG> {
389        self.variant(Idselect::Evsys5)
390    }
391    #[doc = "EVSYS_6"]
392    #[inline(always)]
393    pub fn evsys_6(self) -> &'a mut crate::W<REG> {
394        self.variant(Idselect::Evsys6)
395    }
396    #[doc = "EVSYS_7"]
397    #[inline(always)]
398    pub fn evsys_7(self) -> &'a mut crate::W<REG> {
399        self.variant(Idselect::Evsys7)
400    }
401    #[doc = "EVSYS_8"]
402    #[inline(always)]
403    pub fn evsys_8(self) -> &'a mut crate::W<REG> {
404        self.variant(Idselect::Evsys8)
405    }
406    #[doc = "EVSYS_9"]
407    #[inline(always)]
408    pub fn evsys_9(self) -> &'a mut crate::W<REG> {
409        self.variant(Idselect::Evsys9)
410    }
411    #[doc = "EVSYS_10"]
412    #[inline(always)]
413    pub fn evsys_10(self) -> &'a mut crate::W<REG> {
414        self.variant(Idselect::Evsys10)
415    }
416    #[doc = "EVSYS_11"]
417    #[inline(always)]
418    pub fn evsys_11(self) -> &'a mut crate::W<REG> {
419        self.variant(Idselect::Evsys11)
420    }
421    #[doc = "SERCOMX_SLOW"]
422    #[inline(always)]
423    pub fn sercomx_slow(self) -> &'a mut crate::W<REG> {
424        self.variant(Idselect::SercomxSlow)
425    }
426    #[doc = "SERCOM0_CORE"]
427    #[inline(always)]
428    pub fn sercom0_core(self) -> &'a mut crate::W<REG> {
429        self.variant(Idselect::Sercom0Core)
430    }
431    #[doc = "SERCOM1_CORE"]
432    #[inline(always)]
433    pub fn sercom1_core(self) -> &'a mut crate::W<REG> {
434        self.variant(Idselect::Sercom1Core)
435    }
436    #[doc = "SERCOM2_CORE"]
437    #[inline(always)]
438    pub fn sercom2_core(self) -> &'a mut crate::W<REG> {
439        self.variant(Idselect::Sercom2Core)
440    }
441    #[doc = "SERCOM3_CORE"]
442    #[inline(always)]
443    pub fn sercom3_core(self) -> &'a mut crate::W<REG> {
444        self.variant(Idselect::Sercom3Core)
445    }
446    #[doc = "SERCOM4_CORE"]
447    #[inline(always)]
448    pub fn sercom4_core(self) -> &'a mut crate::W<REG> {
449        self.variant(Idselect::Sercom4Core)
450    }
451    #[doc = "SERCOM5_CORE"]
452    #[inline(always)]
453    pub fn sercom5_core(self) -> &'a mut crate::W<REG> {
454        self.variant(Idselect::Sercom5Core)
455    }
456    #[doc = "TCC0_TCC1"]
457    #[inline(always)]
458    pub fn tcc0_tcc1(self) -> &'a mut crate::W<REG> {
459        self.variant(Idselect::Tcc0Tcc1)
460    }
461    #[doc = "TCC2_TC3"]
462    #[inline(always)]
463    pub fn tcc2_tc3(self) -> &'a mut crate::W<REG> {
464        self.variant(Idselect::Tcc2Tc3)
465    }
466    #[doc = "TC4_TC5"]
467    #[inline(always)]
468    pub fn tc4_tc5(self) -> &'a mut crate::W<REG> {
469        self.variant(Idselect::Tc4Tc5)
470    }
471    #[doc = "TC6_TC7"]
472    #[inline(always)]
473    pub fn tc6_tc7(self) -> &'a mut crate::W<REG> {
474        self.variant(Idselect::Tc6Tc7)
475    }
476    #[doc = "ADC"]
477    #[inline(always)]
478    pub fn adc(self) -> &'a mut crate::W<REG> {
479        self.variant(Idselect::Adc)
480    }
481    #[doc = "AC_DIG"]
482    #[inline(always)]
483    pub fn ac_dig(self) -> &'a mut crate::W<REG> {
484        self.variant(Idselect::AcDig)
485    }
486    #[doc = "AC_ANA"]
487    #[inline(always)]
488    pub fn ac_ana(self) -> &'a mut crate::W<REG> {
489        self.variant(Idselect::AcAna)
490    }
491    #[doc = "DAC"]
492    #[inline(always)]
493    pub fn dac(self) -> &'a mut crate::W<REG> {
494        self.variant(Idselect::Dac)
495    }
496    #[doc = "I2S_0"]
497    #[inline(always)]
498    pub fn i2s_0(self) -> &'a mut crate::W<REG> {
499        self.variant(Idselect::I2s0)
500    }
501    #[doc = "I2S_1"]
502    #[inline(always)]
503    pub fn i2s_1(self) -> &'a mut crate::W<REG> {
504        self.variant(Idselect::I2s1)
505    }
506}
507#[doc = "Generic Clock Generator\n\nValue on reset: 0"]
508#[derive(Clone, Copy, Debug, PartialEq, Eq)]
509#[repr(u8)]
510pub enum Genselect {
511    #[doc = "0: Generic clock generator 0"]
512    Gclk0 = 0,
513    #[doc = "1: Generic clock generator 1"]
514    Gclk1 = 1,
515    #[doc = "2: Generic clock generator 2"]
516    Gclk2 = 2,
517    #[doc = "3: Generic clock generator 3"]
518    Gclk3 = 3,
519    #[doc = "4: Generic clock generator 4"]
520    Gclk4 = 4,
521    #[doc = "5: Generic clock generator 5"]
522    Gclk5 = 5,
523    #[doc = "6: Generic clock generator 6"]
524    Gclk6 = 6,
525    #[doc = "7: Generic clock generator 7"]
526    Gclk7 = 7,
527    #[doc = "8: Generic clock generator 8"]
528    Gclk8 = 8,
529}
530impl From<Genselect> for u8 {
531    #[inline(always)]
532    fn from(variant: Genselect) -> Self {
533        variant as _
534    }
535}
536impl crate::FieldSpec for Genselect {
537    type Ux = u8;
538}
539impl crate::IsEnum for Genselect {}
540#[doc = "Field `GEN` reader - Generic Clock Generator"]
541pub type GenR = crate::FieldReader<Genselect>;
542impl GenR {
543    #[doc = "Get enumerated values variant"]
544    #[inline(always)]
545    pub const fn variant(&self) -> Option<Genselect> {
546        match self.bits {
547            0 => Some(Genselect::Gclk0),
548            1 => Some(Genselect::Gclk1),
549            2 => Some(Genselect::Gclk2),
550            3 => Some(Genselect::Gclk3),
551            4 => Some(Genselect::Gclk4),
552            5 => Some(Genselect::Gclk5),
553            6 => Some(Genselect::Gclk6),
554            7 => Some(Genselect::Gclk7),
555            8 => Some(Genselect::Gclk8),
556            _ => None,
557        }
558    }
559    #[doc = "Generic clock generator 0"]
560    #[inline(always)]
561    pub fn is_gclk0(&self) -> bool {
562        *self == Genselect::Gclk0
563    }
564    #[doc = "Generic clock generator 1"]
565    #[inline(always)]
566    pub fn is_gclk1(&self) -> bool {
567        *self == Genselect::Gclk1
568    }
569    #[doc = "Generic clock generator 2"]
570    #[inline(always)]
571    pub fn is_gclk2(&self) -> bool {
572        *self == Genselect::Gclk2
573    }
574    #[doc = "Generic clock generator 3"]
575    #[inline(always)]
576    pub fn is_gclk3(&self) -> bool {
577        *self == Genselect::Gclk3
578    }
579    #[doc = "Generic clock generator 4"]
580    #[inline(always)]
581    pub fn is_gclk4(&self) -> bool {
582        *self == Genselect::Gclk4
583    }
584    #[doc = "Generic clock generator 5"]
585    #[inline(always)]
586    pub fn is_gclk5(&self) -> bool {
587        *self == Genselect::Gclk5
588    }
589    #[doc = "Generic clock generator 6"]
590    #[inline(always)]
591    pub fn is_gclk6(&self) -> bool {
592        *self == Genselect::Gclk6
593    }
594    #[doc = "Generic clock generator 7"]
595    #[inline(always)]
596    pub fn is_gclk7(&self) -> bool {
597        *self == Genselect::Gclk7
598    }
599    #[doc = "Generic clock generator 8"]
600    #[inline(always)]
601    pub fn is_gclk8(&self) -> bool {
602        *self == Genselect::Gclk8
603    }
604}
605#[doc = "Field `GEN` writer - Generic Clock Generator"]
606pub type GenW<'a, REG> = crate::FieldWriter<'a, REG, 4, Genselect>;
607impl<'a, REG> GenW<'a, REG>
608where
609    REG: crate::Writable + crate::RegisterSpec,
610    REG::Ux: From<u8>,
611{
612    #[doc = "Generic clock generator 0"]
613    #[inline(always)]
614    pub fn gclk0(self) -> &'a mut crate::W<REG> {
615        self.variant(Genselect::Gclk0)
616    }
617    #[doc = "Generic clock generator 1"]
618    #[inline(always)]
619    pub fn gclk1(self) -> &'a mut crate::W<REG> {
620        self.variant(Genselect::Gclk1)
621    }
622    #[doc = "Generic clock generator 2"]
623    #[inline(always)]
624    pub fn gclk2(self) -> &'a mut crate::W<REG> {
625        self.variant(Genselect::Gclk2)
626    }
627    #[doc = "Generic clock generator 3"]
628    #[inline(always)]
629    pub fn gclk3(self) -> &'a mut crate::W<REG> {
630        self.variant(Genselect::Gclk3)
631    }
632    #[doc = "Generic clock generator 4"]
633    #[inline(always)]
634    pub fn gclk4(self) -> &'a mut crate::W<REG> {
635        self.variant(Genselect::Gclk4)
636    }
637    #[doc = "Generic clock generator 5"]
638    #[inline(always)]
639    pub fn gclk5(self) -> &'a mut crate::W<REG> {
640        self.variant(Genselect::Gclk5)
641    }
642    #[doc = "Generic clock generator 6"]
643    #[inline(always)]
644    pub fn gclk6(self) -> &'a mut crate::W<REG> {
645        self.variant(Genselect::Gclk6)
646    }
647    #[doc = "Generic clock generator 7"]
648    #[inline(always)]
649    pub fn gclk7(self) -> &'a mut crate::W<REG> {
650        self.variant(Genselect::Gclk7)
651    }
652    #[doc = "Generic clock generator 8"]
653    #[inline(always)]
654    pub fn gclk8(self) -> &'a mut crate::W<REG> {
655        self.variant(Genselect::Gclk8)
656    }
657}
658#[doc = "Field `CLKEN` reader - Clock Enable"]
659pub type ClkenR = crate::BitReader;
660#[doc = "Field `CLKEN` writer - Clock Enable"]
661pub type ClkenW<'a, REG> = crate::BitWriter<'a, REG>;
662#[doc = "Field `WRTLOCK` reader - Write Lock"]
663pub type WrtlockR = crate::BitReader;
664#[doc = "Field `WRTLOCK` writer - Write Lock"]
665pub type WrtlockW<'a, REG> = crate::BitWriter<'a, REG>;
666impl R {
667    #[doc = "Bits 0:5 - Generic Clock Selection ID"]
668    #[inline(always)]
669    pub fn id(&self) -> IdR {
670        IdR::new((self.bits & 0x3f) as u8)
671    }
672    #[doc = "Bits 8:11 - Generic Clock Generator"]
673    #[inline(always)]
674    pub fn gen(&self) -> GenR {
675        GenR::new(((self.bits >> 8) & 0x0f) as u8)
676    }
677    #[doc = "Bit 14 - Clock Enable"]
678    #[inline(always)]
679    pub fn clken(&self) -> ClkenR {
680        ClkenR::new(((self.bits >> 14) & 1) != 0)
681    }
682    #[doc = "Bit 15 - Write Lock"]
683    #[inline(always)]
684    pub fn wrtlock(&self) -> WrtlockR {
685        WrtlockR::new(((self.bits >> 15) & 1) != 0)
686    }
687}
688impl W {
689    #[doc = "Bits 0:5 - Generic Clock Selection ID"]
690    #[inline(always)]
691    #[must_use]
692    pub fn id(&mut self) -> IdW<ClkctrlSpec> {
693        IdW::new(self, 0)
694    }
695    #[doc = "Bits 8:11 - Generic Clock Generator"]
696    #[inline(always)]
697    #[must_use]
698    pub fn gen(&mut self) -> GenW<ClkctrlSpec> {
699        GenW::new(self, 8)
700    }
701    #[doc = "Bit 14 - Clock Enable"]
702    #[inline(always)]
703    #[must_use]
704    pub fn clken(&mut self) -> ClkenW<ClkctrlSpec> {
705        ClkenW::new(self, 14)
706    }
707    #[doc = "Bit 15 - Write Lock"]
708    #[inline(always)]
709    #[must_use]
710    pub fn wrtlock(&mut self) -> WrtlockW<ClkctrlSpec> {
711        WrtlockW::new(self, 15)
712    }
713}
714#[doc = "Generic Clock Control\n\nYou can [`read`](crate::Reg::read) this register and get [`clkctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clkctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
715pub struct ClkctrlSpec;
716impl crate::RegisterSpec for ClkctrlSpec {
717    type Ux = u16;
718}
719#[doc = "`read()` method returns [`clkctrl::R`](R) reader structure"]
720impl crate::Readable for ClkctrlSpec {}
721#[doc = "`write(|w| ..)` method takes [`clkctrl::W`](W) writer structure"]
722impl crate::Writable for ClkctrlSpec {
723    type Safety = crate::Unsafe;
724    const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0;
725    const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0;
726}
727#[doc = "`reset()` method sets CLKCTRL to value 0"]
728impl crate::Resettable for ClkctrlSpec {
729    const RESET_VALUE: u16 = 0;
730}
atsamd21g/gclk/clkctrl.rs

atsamd21g/gclk/
clkctrl.rs
