atsamd21g/usb/host/
pintenclr.rs

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1#[doc = "Register `PINTENCLR%s` reader"]
2pub type R = crate::R<PintenclrSpec>;
3#[doc = "Register `PINTENCLR%s` writer"]
4pub type W = crate::W<PintenclrSpec>;
5#[doc = "Field `TRCPT0` reader - Transfer Complete 0 Disable"]
6pub type Trcpt0R = crate::BitReader;
7#[doc = "Field `TRCPT0` writer - Transfer Complete 0 Disable"]
8pub type Trcpt0W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `TRCPT1` reader - Transfer Complete 1 Disable"]
10pub type Trcpt1R = crate::BitReader;
11#[doc = "Field `TRCPT1` writer - Transfer Complete 1 Disable"]
12pub type Trcpt1W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `TRFAIL` reader - Error Flow Interrupt Disable"]
14pub type TrfailR = crate::BitReader;
15#[doc = "Field `TRFAIL` writer - Error Flow Interrupt Disable"]
16pub type TrfailW<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `PERR` reader - Pipe Error Interrupt Disable"]
18pub type PerrR = crate::BitReader;
19#[doc = "Field `PERR` writer - Pipe Error Interrupt Disable"]
20pub type PerrW<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `TXSTP` reader - Transmit Setup Interrupt Disable"]
22pub type TxstpR = crate::BitReader;
23#[doc = "Field `TXSTP` writer - Transmit Setup Interrupt Disable"]
24pub type TxstpW<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `STALL` reader - Stall Inetrrupt Disable"]
26pub type StallR = crate::BitReader;
27#[doc = "Field `STALL` writer - Stall Inetrrupt Disable"]
28pub type StallW<'a, REG> = crate::BitWriter<'a, REG>;
29impl R {
30    #[doc = "Bit 0 - Transfer Complete 0 Disable"]
31    #[inline(always)]
32    pub fn trcpt0(&self) -> Trcpt0R {
33        Trcpt0R::new((self.bits & 1) != 0)
34    }
35    #[doc = "Bit 1 - Transfer Complete 1 Disable"]
36    #[inline(always)]
37    pub fn trcpt1(&self) -> Trcpt1R {
38        Trcpt1R::new(((self.bits >> 1) & 1) != 0)
39    }
40    #[doc = "Bit 2 - Error Flow Interrupt Disable"]
41    #[inline(always)]
42    pub fn trfail(&self) -> TrfailR {
43        TrfailR::new(((self.bits >> 2) & 1) != 0)
44    }
45    #[doc = "Bit 3 - Pipe Error Interrupt Disable"]
46    #[inline(always)]
47    pub fn perr(&self) -> PerrR {
48        PerrR::new(((self.bits >> 3) & 1) != 0)
49    }
50    #[doc = "Bit 4 - Transmit Setup Interrupt Disable"]
51    #[inline(always)]
52    pub fn txstp(&self) -> TxstpR {
53        TxstpR::new(((self.bits >> 4) & 1) != 0)
54    }
55    #[doc = "Bit 5 - Stall Inetrrupt Disable"]
56    #[inline(always)]
57    pub fn stall(&self) -> StallR {
58        StallR::new(((self.bits >> 5) & 1) != 0)
59    }
60}
61impl W {
62    #[doc = "Bit 0 - Transfer Complete 0 Disable"]
63    #[inline(always)]
64    #[must_use]
65    pub fn trcpt0(&mut self) -> Trcpt0W<PintenclrSpec> {
66        Trcpt0W::new(self, 0)
67    }
68    #[doc = "Bit 1 - Transfer Complete 1 Disable"]
69    #[inline(always)]
70    #[must_use]
71    pub fn trcpt1(&mut self) -> Trcpt1W<PintenclrSpec> {
72        Trcpt1W::new(self, 1)
73    }
74    #[doc = "Bit 2 - Error Flow Interrupt Disable"]
75    #[inline(always)]
76    #[must_use]
77    pub fn trfail(&mut self) -> TrfailW<PintenclrSpec> {
78        TrfailW::new(self, 2)
79    }
80    #[doc = "Bit 3 - Pipe Error Interrupt Disable"]
81    #[inline(always)]
82    #[must_use]
83    pub fn perr(&mut self) -> PerrW<PintenclrSpec> {
84        PerrW::new(self, 3)
85    }
86    #[doc = "Bit 4 - Transmit Setup Interrupt Disable"]
87    #[inline(always)]
88    #[must_use]
89    pub fn txstp(&mut self) -> TxstpW<PintenclrSpec> {
90        TxstpW::new(self, 4)
91    }
92    #[doc = "Bit 5 - Stall Inetrrupt Disable"]
93    #[inline(always)]
94    #[must_use]
95    pub fn stall(&mut self) -> StallW<PintenclrSpec> {
96        StallW::new(self, 5)
97    }
98}
99#[doc = "HOST Pipe Interrupt Flag Clear\n\nYou can [`read`](crate::Reg::read) this register and get [`pintenclr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pintenclr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
100pub struct PintenclrSpec;
101impl crate::RegisterSpec for PintenclrSpec {
102    type Ux = u8;
103}
104#[doc = "`read()` method returns [`pintenclr::R`](R) reader structure"]
105impl crate::Readable for PintenclrSpec {}
106#[doc = "`write(|w| ..)` method takes [`pintenclr::W`](W) writer structure"]
107impl crate::Writable for PintenclrSpec {
108    type Safety = crate::Unsafe;
109    const ZERO_TO_MODIFY_FIELDS_BITMAP: u8 = 0;
110    const ONE_TO_MODIFY_FIELDS_BITMAP: u8 = 0;
111}
112#[doc = "`reset()` method sets PINTENCLR%s to value 0"]
113impl crate::Resettable for PintenclrSpec {
114    const RESET_VALUE: u8 = 0;
115}
atsamd21g/usb/host/pintenclr.rs

atsamd21g/usb/host/
pintenclr.rs
