atsamd21g/sercom0/i2cm/
ctrla.rs

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1#[doc = "Register `CTRLA` reader"]
2pub type R = crate::R<CtrlaSpec>;
3#[doc = "Register `CTRLA` writer"]
4pub type W = crate::W<CtrlaSpec>;
5#[doc = "Field `SWRST` reader - Software Reset"]
6pub type SwrstR = crate::BitReader;
7#[doc = "Field `SWRST` writer - Software Reset"]
8pub type SwrstW<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `ENABLE` reader - Enable"]
10pub type EnableR = crate::BitReader;
11#[doc = "Field `ENABLE` writer - Enable"]
12pub type EnableW<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Operating Mode\n\nValue on reset: 0"]
14#[derive(Clone, Copy, Debug, PartialEq, Eq)]
15#[repr(u8)]
16pub enum Modeselect {
17    #[doc = "0: USART mode with external clock"]
18    UsartExtClk = 0,
19    #[doc = "1: USART mode with internal clock"]
20    UsartIntClk = 1,
21    #[doc = "2: SPI mode with external clock"]
22    SpiSlave = 2,
23    #[doc = "3: SPI mode with internal clock"]
24    SpiMaster = 3,
25    #[doc = "4: I2C mode with external clock"]
26    I2cSlave = 4,
27    #[doc = "5: I2C mode with internal clock"]
28    I2cMaster = 5,
29}
30impl From<Modeselect> for u8 {
31    #[inline(always)]
32    fn from(variant: Modeselect) -> Self {
33        variant as _
34    }
35}
36impl crate::FieldSpec for Modeselect {
37    type Ux = u8;
38}
39impl crate::IsEnum for Modeselect {}
40#[doc = "Field `MODE` reader - Operating Mode"]
41pub type ModeR = crate::FieldReader<Modeselect>;
42impl ModeR {
43    #[doc = "Get enumerated values variant"]
44    #[inline(always)]
45    pub const fn variant(&self) -> Option<Modeselect> {
46        match self.bits {
47            0 => Some(Modeselect::UsartExtClk),
48            1 => Some(Modeselect::UsartIntClk),
49            2 => Some(Modeselect::SpiSlave),
50            3 => Some(Modeselect::SpiMaster),
51            4 => Some(Modeselect::I2cSlave),
52            5 => Some(Modeselect::I2cMaster),
53            _ => None,
54        }
55    }
56    #[doc = "USART mode with external clock"]
57    #[inline(always)]
58    pub fn is_usart_ext_clk(&self) -> bool {
59        *self == Modeselect::UsartExtClk
60    }
61    #[doc = "USART mode with internal clock"]
62    #[inline(always)]
63    pub fn is_usart_int_clk(&self) -> bool {
64        *self == Modeselect::UsartIntClk
65    }
66    #[doc = "SPI mode with external clock"]
67    #[inline(always)]
68    pub fn is_spi_slave(&self) -> bool {
69        *self == Modeselect::SpiSlave
70    }
71    #[doc = "SPI mode with internal clock"]
72    #[inline(always)]
73    pub fn is_spi_master(&self) -> bool {
74        *self == Modeselect::SpiMaster
75    }
76    #[doc = "I2C mode with external clock"]
77    #[inline(always)]
78    pub fn is_i2c_slave(&self) -> bool {
79        *self == Modeselect::I2cSlave
80    }
81    #[doc = "I2C mode with internal clock"]
82    #[inline(always)]
83    pub fn is_i2c_master(&self) -> bool {
84        *self == Modeselect::I2cMaster
85    }
86}
87#[doc = "Field `MODE` writer - Operating Mode"]
88pub type ModeW<'a, REG> = crate::FieldWriter<'a, REG, 3, Modeselect>;
89impl<'a, REG> ModeW<'a, REG>
90where
91    REG: crate::Writable + crate::RegisterSpec,
92    REG::Ux: From<u8>,
93{
94    #[doc = "USART mode with external clock"]
95    #[inline(always)]
96    pub fn usart_ext_clk(self) -> &'a mut crate::W<REG> {
97        self.variant(Modeselect::UsartExtClk)
98    }
99    #[doc = "USART mode with internal clock"]
100    #[inline(always)]
101    pub fn usart_int_clk(self) -> &'a mut crate::W<REG> {
102        self.variant(Modeselect::UsartIntClk)
103    }
104    #[doc = "SPI mode with external clock"]
105    #[inline(always)]
106    pub fn spi_slave(self) -> &'a mut crate::W<REG> {
107        self.variant(Modeselect::SpiSlave)
108    }
109    #[doc = "SPI mode with internal clock"]
110    #[inline(always)]
111    pub fn spi_master(self) -> &'a mut crate::W<REG> {
112        self.variant(Modeselect::SpiMaster)
113    }
114    #[doc = "I2C mode with external clock"]
115    #[inline(always)]
116    pub fn i2c_slave(self) -> &'a mut crate::W<REG> {
117        self.variant(Modeselect::I2cSlave)
118    }
119    #[doc = "I2C mode with internal clock"]
120    #[inline(always)]
121    pub fn i2c_master(self) -> &'a mut crate::W<REG> {
122        self.variant(Modeselect::I2cMaster)
123    }
124}
125#[doc = "Field `RUNSTDBY` reader - Run in Standby"]
126pub type RunstdbyR = crate::BitReader;
127#[doc = "Field `RUNSTDBY` writer - Run in Standby"]
128pub type RunstdbyW<'a, REG> = crate::BitWriter<'a, REG>;
129#[doc = "Field `PINOUT` reader - Pin Usage"]
130pub type PinoutR = crate::BitReader;
131#[doc = "Field `PINOUT` writer - Pin Usage"]
132pub type PinoutW<'a, REG> = crate::BitWriter<'a, REG>;
133#[doc = "Field `SDAHOLD` reader - SDA Hold Time"]
134pub type SdaholdR = crate::FieldReader;
135#[doc = "Field `SDAHOLD` writer - SDA Hold Time"]
136pub type SdaholdW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
137#[doc = "Field `MEXTTOEN` reader - Master SCL Low Extend Timeout"]
138pub type MexttoenR = crate::BitReader;
139#[doc = "Field `MEXTTOEN` writer - Master SCL Low Extend Timeout"]
140pub type MexttoenW<'a, REG> = crate::BitWriter<'a, REG>;
141#[doc = "Field `SEXTTOEN` reader - Slave SCL Low Extend Timeout"]
142pub type SexttoenR = crate::BitReader;
143#[doc = "Field `SEXTTOEN` writer - Slave SCL Low Extend Timeout"]
144pub type SexttoenW<'a, REG> = crate::BitWriter<'a, REG>;
145#[doc = "Field `SPEED` reader - Transfer Speed"]
146pub type SpeedR = crate::FieldReader;
147#[doc = "Field `SPEED` writer - Transfer Speed"]
148pub type SpeedW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
149#[doc = "Field `SCLSM` reader - SCL Clock Stretch Mode"]
150pub type SclsmR = crate::BitReader;
151#[doc = "Field `SCLSM` writer - SCL Clock Stretch Mode"]
152pub type SclsmW<'a, REG> = crate::BitWriter<'a, REG>;
153#[doc = "Field `INACTOUT` reader - Inactive Time-Out"]
154pub type InactoutR = crate::FieldReader;
155#[doc = "Field `INACTOUT` writer - Inactive Time-Out"]
156pub type InactoutW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
157#[doc = "Field `LOWTOUTEN` reader - SCL Low Timeout Enable"]
158pub type LowtoutenR = crate::BitReader;
159#[doc = "Field `LOWTOUTEN` writer - SCL Low Timeout Enable"]
160pub type LowtoutenW<'a, REG> = crate::BitWriter<'a, REG>;
161impl R {
162    #[doc = "Bit 0 - Software Reset"]
163    #[inline(always)]
164    pub fn swrst(&self) -> SwrstR {
165        SwrstR::new((self.bits & 1) != 0)
166    }
167    #[doc = "Bit 1 - Enable"]
168    #[inline(always)]
169    pub fn enable(&self) -> EnableR {
170        EnableR::new(((self.bits >> 1) & 1) != 0)
171    }
172    #[doc = "Bits 2:4 - Operating Mode"]
173    #[inline(always)]
174    pub fn mode(&self) -> ModeR {
175        ModeR::new(((self.bits >> 2) & 7) as u8)
176    }
177    #[doc = "Bit 7 - Run in Standby"]
178    #[inline(always)]
179    pub fn runstdby(&self) -> RunstdbyR {
180        RunstdbyR::new(((self.bits >> 7) & 1) != 0)
181    }
182    #[doc = "Bit 16 - Pin Usage"]
183    #[inline(always)]
184    pub fn pinout(&self) -> PinoutR {
185        PinoutR::new(((self.bits >> 16) & 1) != 0)
186    }
187    #[doc = "Bits 20:21 - SDA Hold Time"]
188    #[inline(always)]
189    pub fn sdahold(&self) -> SdaholdR {
190        SdaholdR::new(((self.bits >> 20) & 3) as u8)
191    }
192    #[doc = "Bit 22 - Master SCL Low Extend Timeout"]
193    #[inline(always)]
194    pub fn mexttoen(&self) -> MexttoenR {
195        MexttoenR::new(((self.bits >> 22) & 1) != 0)
196    }
197    #[doc = "Bit 23 - Slave SCL Low Extend Timeout"]
198    #[inline(always)]
199    pub fn sexttoen(&self) -> SexttoenR {
200        SexttoenR::new(((self.bits >> 23) & 1) != 0)
201    }
202    #[doc = "Bits 24:25 - Transfer Speed"]
203    #[inline(always)]
204    pub fn speed(&self) -> SpeedR {
205        SpeedR::new(((self.bits >> 24) & 3) as u8)
206    }
207    #[doc = "Bit 27 - SCL Clock Stretch Mode"]
208    #[inline(always)]
209    pub fn sclsm(&self) -> SclsmR {
210        SclsmR::new(((self.bits >> 27) & 1) != 0)
211    }
212    #[doc = "Bits 28:29 - Inactive Time-Out"]
213    #[inline(always)]
214    pub fn inactout(&self) -> InactoutR {
215        InactoutR::new(((self.bits >> 28) & 3) as u8)
216    }
217    #[doc = "Bit 30 - SCL Low Timeout Enable"]
218    #[inline(always)]
219    pub fn lowtouten(&self) -> LowtoutenR {
220        LowtoutenR::new(((self.bits >> 30) & 1) != 0)
221    }
222}
223impl W {
224    #[doc = "Bit 0 - Software Reset"]
225    #[inline(always)]
226    #[must_use]
227    pub fn swrst(&mut self) -> SwrstW<CtrlaSpec> {
228        SwrstW::new(self, 0)
229    }
230    #[doc = "Bit 1 - Enable"]
231    #[inline(always)]
232    #[must_use]
233    pub fn enable(&mut self) -> EnableW<CtrlaSpec> {
234        EnableW::new(self, 1)
235    }
236    #[doc = "Bits 2:4 - Operating Mode"]
237    #[inline(always)]
238    #[must_use]
239    pub fn mode(&mut self) -> ModeW<CtrlaSpec> {
240        ModeW::new(self, 2)
241    }
242    #[doc = "Bit 7 - Run in Standby"]
243    #[inline(always)]
244    #[must_use]
245    pub fn runstdby(&mut self) -> RunstdbyW<CtrlaSpec> {
246        RunstdbyW::new(self, 7)
247    }
248    #[doc = "Bit 16 - Pin Usage"]
249    #[inline(always)]
250    #[must_use]
251    pub fn pinout(&mut self) -> PinoutW<CtrlaSpec> {
252        PinoutW::new(self, 16)
253    }
254    #[doc = "Bits 20:21 - SDA Hold Time"]
255    #[inline(always)]
256    #[must_use]
257    pub fn sdahold(&mut self) -> SdaholdW<CtrlaSpec> {
258        SdaholdW::new(self, 20)
259    }
260    #[doc = "Bit 22 - Master SCL Low Extend Timeout"]
261    #[inline(always)]
262    #[must_use]
263    pub fn mexttoen(&mut self) -> MexttoenW<CtrlaSpec> {
264        MexttoenW::new(self, 22)
265    }
266    #[doc = "Bit 23 - Slave SCL Low Extend Timeout"]
267    #[inline(always)]
268    #[must_use]
269    pub fn sexttoen(&mut self) -> SexttoenW<CtrlaSpec> {
270        SexttoenW::new(self, 23)
271    }
272    #[doc = "Bits 24:25 - Transfer Speed"]
273    #[inline(always)]
274    #[must_use]
275    pub fn speed(&mut self) -> SpeedW<CtrlaSpec> {
276        SpeedW::new(self, 24)
277    }
278    #[doc = "Bit 27 - SCL Clock Stretch Mode"]
279    #[inline(always)]
280    #[must_use]
281    pub fn sclsm(&mut self) -> SclsmW<CtrlaSpec> {
282        SclsmW::new(self, 27)
283    }
284    #[doc = "Bits 28:29 - Inactive Time-Out"]
285    #[inline(always)]
286    #[must_use]
287    pub fn inactout(&mut self) -> InactoutW<CtrlaSpec> {
288        InactoutW::new(self, 28)
289    }
290    #[doc = "Bit 30 - SCL Low Timeout Enable"]
291    #[inline(always)]
292    #[must_use]
293    pub fn lowtouten(&mut self) -> LowtoutenW<CtrlaSpec> {
294        LowtoutenW::new(self, 30)
295    }
296}
297#[doc = "I2CM Control A\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrla::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrla::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
298pub struct CtrlaSpec;
299impl crate::RegisterSpec for CtrlaSpec {
300    type Ux = u32;
301}
302#[doc = "`read()` method returns [`ctrla::R`](R) reader structure"]
303impl crate::Readable for CtrlaSpec {}
304#[doc = "`write(|w| ..)` method takes [`ctrla::W`](W) writer structure"]
305impl crate::Writable for CtrlaSpec {
306    type Safety = crate::Unsafe;
307    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
308    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
309}
310#[doc = "`reset()` method sets CTRLA to value 0"]
311impl crate::Resettable for CtrlaSpec {
312    const RESET_VALUE: u32 = 0;
313}
atsamd21g/sercom0/i2cm/ctrla.rs

atsamd21g/sercom0/i2cm/
ctrla.rs
