atsamd21g/wdt/
intenclr.rs

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1#[doc = "Register `INTENCLR` reader"]
2pub type R = crate::R<IntenclrSpec>;
3#[doc = "Register `INTENCLR` writer"]
4pub type W = crate::W<IntenclrSpec>;
5#[doc = "Field `EW` reader - Early Warning Interrupt Enable"]
6pub type EwR = crate::BitReader;
7#[doc = "Field `EW` writer - Early Warning Interrupt Enable"]
8pub type EwW<'a, REG> = crate::BitWriter<'a, REG>;
9impl R {
10    #[doc = "Bit 0 - Early Warning Interrupt Enable"]
11    #[inline(always)]
12    pub fn ew(&self) -> EwR {
13        EwR::new((self.bits & 1) != 0)
14    }
15}
16impl W {
17    #[doc = "Bit 0 - Early Warning Interrupt Enable"]
18    #[inline(always)]
19    #[must_use]
20    pub fn ew(&mut self) -> EwW<IntenclrSpec> {
21        EwW::new(self, 0)
22    }
23}
24#[doc = "Interrupt Enable Clear\n\nYou can [`read`](crate::Reg::read) this register and get [`intenclr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intenclr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
25pub struct IntenclrSpec;
26impl crate::RegisterSpec for IntenclrSpec {
27    type Ux = u8;
28}
29#[doc = "`read()` method returns [`intenclr::R`](R) reader structure"]
30impl crate::Readable for IntenclrSpec {}
31#[doc = "`write(|w| ..)` method takes [`intenclr::W`](W) writer structure"]
32impl crate::Writable for IntenclrSpec {
33    type Safety = crate::Unsafe;
34    const ZERO_TO_MODIFY_FIELDS_BITMAP: u8 = 0;
35    const ONE_TO_MODIFY_FIELDS_BITMAP: u8 = 0;
36}
37#[doc = "`reset()` method sets INTENCLR to value 0"]
38impl crate::Resettable for IntenclrSpec {
39    const RESET_VALUE: u8 = 0;
40}
atsamd21g/wdt/intenclr.rs

atsamd21g/wdt/
intenclr.rs
