atsamd21g/sercom0/usart/
intenclr.rs

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1#[doc = "Register `INTENCLR` reader"]
2pub type R = crate::R<IntenclrSpec>;
3#[doc = "Register `INTENCLR` writer"]
4pub type W = crate::W<IntenclrSpec>;
5#[doc = "Field `DRE` reader - Data Register Empty Interrupt Disable"]
6pub type DreR = crate::BitReader;
7#[doc = "Field `DRE` writer - Data Register Empty Interrupt Disable"]
8pub type DreW<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `TXC` reader - Transmit Complete Interrupt Disable"]
10pub type TxcR = crate::BitReader;
11#[doc = "Field `TXC` writer - Transmit Complete Interrupt Disable"]
12pub type TxcW<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `RXC` reader - Receive Complete Interrupt Disable"]
14pub type RxcR = crate::BitReader;
15#[doc = "Field `RXC` writer - Receive Complete Interrupt Disable"]
16pub type RxcW<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `RXS` reader - Receive Start Interrupt Disable"]
18pub type RxsR = crate::BitReader;
19#[doc = "Field `RXS` writer - Receive Start Interrupt Disable"]
20pub type RxsW<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `CTSIC` reader - Clear To Send Input Change Interrupt Disable"]
22pub type CtsicR = crate::BitReader;
23#[doc = "Field `CTSIC` writer - Clear To Send Input Change Interrupt Disable"]
24pub type CtsicW<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `RXBRK` reader - Break Received Interrupt Disable"]
26pub type RxbrkR = crate::BitReader;
27#[doc = "Field `RXBRK` writer - Break Received Interrupt Disable"]
28pub type RxbrkW<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `ERROR` reader - Combined Error Interrupt Disable"]
30pub type ErrorR = crate::BitReader;
31#[doc = "Field `ERROR` writer - Combined Error Interrupt Disable"]
32pub type ErrorW<'a, REG> = crate::BitWriter<'a, REG>;
33impl R {
34    #[doc = "Bit 0 - Data Register Empty Interrupt Disable"]
35    #[inline(always)]
36    pub fn dre(&self) -> DreR {
37        DreR::new((self.bits & 1) != 0)
38    }
39    #[doc = "Bit 1 - Transmit Complete Interrupt Disable"]
40    #[inline(always)]
41    pub fn txc(&self) -> TxcR {
42        TxcR::new(((self.bits >> 1) & 1) != 0)
43    }
44    #[doc = "Bit 2 - Receive Complete Interrupt Disable"]
45    #[inline(always)]
46    pub fn rxc(&self) -> RxcR {
47        RxcR::new(((self.bits >> 2) & 1) != 0)
48    }
49    #[doc = "Bit 3 - Receive Start Interrupt Disable"]
50    #[inline(always)]
51    pub fn rxs(&self) -> RxsR {
52        RxsR::new(((self.bits >> 3) & 1) != 0)
53    }
54    #[doc = "Bit 4 - Clear To Send Input Change Interrupt Disable"]
55    #[inline(always)]
56    pub fn ctsic(&self) -> CtsicR {
57        CtsicR::new(((self.bits >> 4) & 1) != 0)
58    }
59    #[doc = "Bit 5 - Break Received Interrupt Disable"]
60    #[inline(always)]
61    pub fn rxbrk(&self) -> RxbrkR {
62        RxbrkR::new(((self.bits >> 5) & 1) != 0)
63    }
64    #[doc = "Bit 7 - Combined Error Interrupt Disable"]
65    #[inline(always)]
66    pub fn error(&self) -> ErrorR {
67        ErrorR::new(((self.bits >> 7) & 1) != 0)
68    }
69}
70impl W {
71    #[doc = "Bit 0 - Data Register Empty Interrupt Disable"]
72    #[inline(always)]
73    #[must_use]
74    pub fn dre(&mut self) -> DreW<IntenclrSpec> {
75        DreW::new(self, 0)
76    }
77    #[doc = "Bit 1 - Transmit Complete Interrupt Disable"]
78    #[inline(always)]
79    #[must_use]
80    pub fn txc(&mut self) -> TxcW<IntenclrSpec> {
81        TxcW::new(self, 1)
82    }
83    #[doc = "Bit 2 - Receive Complete Interrupt Disable"]
84    #[inline(always)]
85    #[must_use]
86    pub fn rxc(&mut self) -> RxcW<IntenclrSpec> {
87        RxcW::new(self, 2)
88    }
89    #[doc = "Bit 3 - Receive Start Interrupt Disable"]
90    #[inline(always)]
91    #[must_use]
92    pub fn rxs(&mut self) -> RxsW<IntenclrSpec> {
93        RxsW::new(self, 3)
94    }
95    #[doc = "Bit 4 - Clear To Send Input Change Interrupt Disable"]
96    #[inline(always)]
97    #[must_use]
98    pub fn ctsic(&mut self) -> CtsicW<IntenclrSpec> {
99        CtsicW::new(self, 4)
100    }
101    #[doc = "Bit 5 - Break Received Interrupt Disable"]
102    #[inline(always)]
103    #[must_use]
104    pub fn rxbrk(&mut self) -> RxbrkW<IntenclrSpec> {
105        RxbrkW::new(self, 5)
106    }
107    #[doc = "Bit 7 - Combined Error Interrupt Disable"]
108    #[inline(always)]
109    #[must_use]
110    pub fn error(&mut self) -> ErrorW<IntenclrSpec> {
111        ErrorW::new(self, 7)
112    }
113}
114#[doc = "USART Interrupt Enable Clear\n\nYou can [`read`](crate::Reg::read) this register and get [`intenclr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intenclr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
115pub struct IntenclrSpec;
116impl crate::RegisterSpec for IntenclrSpec {
117    type Ux = u8;
118}
119#[doc = "`read()` method returns [`intenclr::R`](R) reader structure"]
120impl crate::Readable for IntenclrSpec {}
121#[doc = "`write(|w| ..)` method takes [`intenclr::W`](W) writer structure"]
122impl crate::Writable for IntenclrSpec {
123    type Safety = crate::Unsafe;
124    const ZERO_TO_MODIFY_FIELDS_BITMAP: u8 = 0;
125    const ONE_TO_MODIFY_FIELDS_BITMAP: u8 = 0;
126}
127#[doc = "`reset()` method sets INTENCLR to value 0"]
128impl crate::Resettable for IntenclrSpec {
129    const RESET_VALUE: u8 = 0;
130}
atsamd21g/sercom0/usart/intenclr.rs

atsamd21g/sercom0/usart/
intenclr.rs
