atsamd21j/sysctrl/
bod33.rs

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1#[doc = "Register `BOD33` reader"]
2pub type R = crate::R<Bod33Spec>;
3#[doc = "Register `BOD33` writer"]
4pub type W = crate::W<Bod33Spec>;
5#[doc = "Field `ENABLE` reader - Enable"]
6pub type EnableR = crate::BitReader;
7#[doc = "Field `ENABLE` writer - Enable"]
8pub type EnableW<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `HYST` reader - Hysteresis"]
10pub type HystR = crate::BitReader;
11#[doc = "Field `HYST` writer - Hysteresis"]
12pub type HystW<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "BOD33 Action\n\nValue on reset: 0"]
14#[derive(Clone, Copy, Debug, PartialEq, Eq)]
15#[repr(u8)]
16pub enum Actionselect {
17    #[doc = "0: No action"]
18    None = 0,
19    #[doc = "1: The BOD33 generates a reset"]
20    Reset = 1,
21    #[doc = "2: The BOD33 generates an interrupt"]
22    Interrupt = 2,
23}
24impl From<Actionselect> for u8 {
25    #[inline(always)]
26    fn from(variant: Actionselect) -> Self {
27        variant as _
28    }
29}
30impl crate::FieldSpec for Actionselect {
31    type Ux = u8;
32}
33impl crate::IsEnum for Actionselect {}
34#[doc = "Field `ACTION` reader - BOD33 Action"]
35pub type ActionR = crate::FieldReader<Actionselect>;
36impl ActionR {
37    #[doc = "Get enumerated values variant"]
38    #[inline(always)]
39    pub const fn variant(&self) -> Option<Actionselect> {
40        match self.bits {
41            0 => Some(Actionselect::None),
42            1 => Some(Actionselect::Reset),
43            2 => Some(Actionselect::Interrupt),
44            _ => None,
45        }
46    }
47    #[doc = "No action"]
48    #[inline(always)]
49    pub fn is_none(&self) -> bool {
50        *self == Actionselect::None
51    }
52    #[doc = "The BOD33 generates a reset"]
53    #[inline(always)]
54    pub fn is_reset(&self) -> bool {
55        *self == Actionselect::Reset
56    }
57    #[doc = "The BOD33 generates an interrupt"]
58    #[inline(always)]
59    pub fn is_interrupt(&self) -> bool {
60        *self == Actionselect::Interrupt
61    }
62}
63#[doc = "Field `ACTION` writer - BOD33 Action"]
64pub type ActionW<'a, REG> = crate::FieldWriter<'a, REG, 2, Actionselect>;
65impl<'a, REG> ActionW<'a, REG>
66where
67    REG: crate::Writable + crate::RegisterSpec,
68    REG::Ux: From<u8>,
69{
70    #[doc = "No action"]
71    #[inline(always)]
72    pub fn none(self) -> &'a mut crate::W<REG> {
73        self.variant(Actionselect::None)
74    }
75    #[doc = "The BOD33 generates a reset"]
76    #[inline(always)]
77    pub fn reset(self) -> &'a mut crate::W<REG> {
78        self.variant(Actionselect::Reset)
79    }
80    #[doc = "The BOD33 generates an interrupt"]
81    #[inline(always)]
82    pub fn interrupt(self) -> &'a mut crate::W<REG> {
83        self.variant(Actionselect::Interrupt)
84    }
85}
86#[doc = "Field `RUNSTDBY` reader - Run in Standby"]
87pub type RunstdbyR = crate::BitReader;
88#[doc = "Field `RUNSTDBY` writer - Run in Standby"]
89pub type RunstdbyW<'a, REG> = crate::BitWriter<'a, REG>;
90#[doc = "Field `MODE` reader - Operation Mode"]
91pub type ModeR = crate::BitReader;
92#[doc = "Field `MODE` writer - Operation Mode"]
93pub type ModeW<'a, REG> = crate::BitWriter<'a, REG>;
94#[doc = "Field `CEN` reader - Clock Enable"]
95pub type CenR = crate::BitReader;
96#[doc = "Field `CEN` writer - Clock Enable"]
97pub type CenW<'a, REG> = crate::BitWriter<'a, REG>;
98#[doc = "Prescaler Select\n\nValue on reset: 0"]
99#[derive(Clone, Copy, Debug, PartialEq, Eq)]
100#[repr(u8)]
101pub enum Pselselect {
102    #[doc = "0: Divide clock by 2"]
103    Div2 = 0,
104    #[doc = "1: Divide clock by 4"]
105    Div4 = 1,
106    #[doc = "2: Divide clock by 8"]
107    Div8 = 2,
108    #[doc = "3: Divide clock by 16"]
109    Div16 = 3,
110    #[doc = "4: Divide clock by 32"]
111    Div32 = 4,
112    #[doc = "5: Divide clock by 64"]
113    Div64 = 5,
114    #[doc = "6: Divide clock by 128"]
115    Div128 = 6,
116    #[doc = "7: Divide clock by 256"]
117    Div256 = 7,
118    #[doc = "8: Divide clock by 512"]
119    Div512 = 8,
120    #[doc = "9: Divide clock by 1024"]
121    Div1k = 9,
122    #[doc = "10: Divide clock by 2048"]
123    Div2k = 10,
124    #[doc = "11: Divide clock by 4096"]
125    Div4k = 11,
126    #[doc = "12: Divide clock by 8192"]
127    Div8k = 12,
128    #[doc = "13: Divide clock by 16384"]
129    Div16k = 13,
130    #[doc = "14: Divide clock by 32768"]
131    Div32k = 14,
132    #[doc = "15: Divide clock by 65536"]
133    Div64k = 15,
134}
135impl From<Pselselect> for u8 {
136    #[inline(always)]
137    fn from(variant: Pselselect) -> Self {
138        variant as _
139    }
140}
141impl crate::FieldSpec for Pselselect {
142    type Ux = u8;
143}
144impl crate::IsEnum for Pselselect {}
145#[doc = "Field `PSEL` reader - Prescaler Select"]
146pub type PselR = crate::FieldReader<Pselselect>;
147impl PselR {
148    #[doc = "Get enumerated values variant"]
149    #[inline(always)]
150    pub const fn variant(&self) -> Pselselect {
151        match self.bits {
152            0 => Pselselect::Div2,
153            1 => Pselselect::Div4,
154            2 => Pselselect::Div8,
155            3 => Pselselect::Div16,
156            4 => Pselselect::Div32,
157            5 => Pselselect::Div64,
158            6 => Pselselect::Div128,
159            7 => Pselselect::Div256,
160            8 => Pselselect::Div512,
161            9 => Pselselect::Div1k,
162            10 => Pselselect::Div2k,
163            11 => Pselselect::Div4k,
164            12 => Pselselect::Div8k,
165            13 => Pselselect::Div16k,
166            14 => Pselselect::Div32k,
167            15 => Pselselect::Div64k,
168            _ => unreachable!(),
169        }
170    }
171    #[doc = "Divide clock by 2"]
172    #[inline(always)]
173    pub fn is_div2(&self) -> bool {
174        *self == Pselselect::Div2
175    }
176    #[doc = "Divide clock by 4"]
177    #[inline(always)]
178    pub fn is_div4(&self) -> bool {
179        *self == Pselselect::Div4
180    }
181    #[doc = "Divide clock by 8"]
182    #[inline(always)]
183    pub fn is_div8(&self) -> bool {
184        *self == Pselselect::Div8
185    }
186    #[doc = "Divide clock by 16"]
187    #[inline(always)]
188    pub fn is_div16(&self) -> bool {
189        *self == Pselselect::Div16
190    }
191    #[doc = "Divide clock by 32"]
192    #[inline(always)]
193    pub fn is_div32(&self) -> bool {
194        *self == Pselselect::Div32
195    }
196    #[doc = "Divide clock by 64"]
197    #[inline(always)]
198    pub fn is_div64(&self) -> bool {
199        *self == Pselselect::Div64
200    }
201    #[doc = "Divide clock by 128"]
202    #[inline(always)]
203    pub fn is_div128(&self) -> bool {
204        *self == Pselselect::Div128
205    }
206    #[doc = "Divide clock by 256"]
207    #[inline(always)]
208    pub fn is_div256(&self) -> bool {
209        *self == Pselselect::Div256
210    }
211    #[doc = "Divide clock by 512"]
212    #[inline(always)]
213    pub fn is_div512(&self) -> bool {
214        *self == Pselselect::Div512
215    }
216    #[doc = "Divide clock by 1024"]
217    #[inline(always)]
218    pub fn is_div1k(&self) -> bool {
219        *self == Pselselect::Div1k
220    }
221    #[doc = "Divide clock by 2048"]
222    #[inline(always)]
223    pub fn is_div2k(&self) -> bool {
224        *self == Pselselect::Div2k
225    }
226    #[doc = "Divide clock by 4096"]
227    #[inline(always)]
228    pub fn is_div4k(&self) -> bool {
229        *self == Pselselect::Div4k
230    }
231    #[doc = "Divide clock by 8192"]
232    #[inline(always)]
233    pub fn is_div8k(&self) -> bool {
234        *self == Pselselect::Div8k
235    }
236    #[doc = "Divide clock by 16384"]
237    #[inline(always)]
238    pub fn is_div16k(&self) -> bool {
239        *self == Pselselect::Div16k
240    }
241    #[doc = "Divide clock by 32768"]
242    #[inline(always)]
243    pub fn is_div32k(&self) -> bool {
244        *self == Pselselect::Div32k
245    }
246    #[doc = "Divide clock by 65536"]
247    #[inline(always)]
248    pub fn is_div64k(&self) -> bool {
249        *self == Pselselect::Div64k
250    }
251}
252#[doc = "Field `PSEL` writer - Prescaler Select"]
253pub type PselW<'a, REG> = crate::FieldWriter<'a, REG, 4, Pselselect, crate::Safe>;
254impl<'a, REG> PselW<'a, REG>
255where
256    REG: crate::Writable + crate::RegisterSpec,
257    REG::Ux: From<u8>,
258{
259    #[doc = "Divide clock by 2"]
260    #[inline(always)]
261    pub fn div2(self) -> &'a mut crate::W<REG> {
262        self.variant(Pselselect::Div2)
263    }
264    #[doc = "Divide clock by 4"]
265    #[inline(always)]
266    pub fn div4(self) -> &'a mut crate::W<REG> {
267        self.variant(Pselselect::Div4)
268    }
269    #[doc = "Divide clock by 8"]
270    #[inline(always)]
271    pub fn div8(self) -> &'a mut crate::W<REG> {
272        self.variant(Pselselect::Div8)
273    }
274    #[doc = "Divide clock by 16"]
275    #[inline(always)]
276    pub fn div16(self) -> &'a mut crate::W<REG> {
277        self.variant(Pselselect::Div16)
278    }
279    #[doc = "Divide clock by 32"]
280    #[inline(always)]
281    pub fn div32(self) -> &'a mut crate::W<REG> {
282        self.variant(Pselselect::Div32)
283    }
284    #[doc = "Divide clock by 64"]
285    #[inline(always)]
286    pub fn div64(self) -> &'a mut crate::W<REG> {
287        self.variant(Pselselect::Div64)
288    }
289    #[doc = "Divide clock by 128"]
290    #[inline(always)]
291    pub fn div128(self) -> &'a mut crate::W<REG> {
292        self.variant(Pselselect::Div128)
293    }
294    #[doc = "Divide clock by 256"]
295    #[inline(always)]
296    pub fn div256(self) -> &'a mut crate::W<REG> {
297        self.variant(Pselselect::Div256)
298    }
299    #[doc = "Divide clock by 512"]
300    #[inline(always)]
301    pub fn div512(self) -> &'a mut crate::W<REG> {
302        self.variant(Pselselect::Div512)
303    }
304    #[doc = "Divide clock by 1024"]
305    #[inline(always)]
306    pub fn div1k(self) -> &'a mut crate::W<REG> {
307        self.variant(Pselselect::Div1k)
308    }
309    #[doc = "Divide clock by 2048"]
310    #[inline(always)]
311    pub fn div2k(self) -> &'a mut crate::W<REG> {
312        self.variant(Pselselect::Div2k)
313    }
314    #[doc = "Divide clock by 4096"]
315    #[inline(always)]
316    pub fn div4k(self) -> &'a mut crate::W<REG> {
317        self.variant(Pselselect::Div4k)
318    }
319    #[doc = "Divide clock by 8192"]
320    #[inline(always)]
321    pub fn div8k(self) -> &'a mut crate::W<REG> {
322        self.variant(Pselselect::Div8k)
323    }
324    #[doc = "Divide clock by 16384"]
325    #[inline(always)]
326    pub fn div16k(self) -> &'a mut crate::W<REG> {
327        self.variant(Pselselect::Div16k)
328    }
329    #[doc = "Divide clock by 32768"]
330    #[inline(always)]
331    pub fn div32k(self) -> &'a mut crate::W<REG> {
332        self.variant(Pselselect::Div32k)
333    }
334    #[doc = "Divide clock by 65536"]
335    #[inline(always)]
336    pub fn div64k(self) -> &'a mut crate::W<REG> {
337        self.variant(Pselselect::Div64k)
338    }
339}
340#[doc = "Field `LEVEL` reader - BOD33 Threshold Level"]
341pub type LevelR = crate::FieldReader;
342#[doc = "Field `LEVEL` writer - BOD33 Threshold Level"]
343pub type LevelW<'a, REG> = crate::FieldWriter<'a, REG, 6>;
344impl R {
345    #[doc = "Bit 1 - Enable"]
346    #[inline(always)]
347    pub fn enable(&self) -> EnableR {
348        EnableR::new(((self.bits >> 1) & 1) != 0)
349    }
350    #[doc = "Bit 2 - Hysteresis"]
351    #[inline(always)]
352    pub fn hyst(&self) -> HystR {
353        HystR::new(((self.bits >> 2) & 1) != 0)
354    }
355    #[doc = "Bits 3:4 - BOD33 Action"]
356    #[inline(always)]
357    pub fn action(&self) -> ActionR {
358        ActionR::new(((self.bits >> 3) & 3) as u8)
359    }
360    #[doc = "Bit 6 - Run in Standby"]
361    #[inline(always)]
362    pub fn runstdby(&self) -> RunstdbyR {
363        RunstdbyR::new(((self.bits >> 6) & 1) != 0)
364    }
365    #[doc = "Bit 8 - Operation Mode"]
366    #[inline(always)]
367    pub fn mode(&self) -> ModeR {
368        ModeR::new(((self.bits >> 8) & 1) != 0)
369    }
370    #[doc = "Bit 9 - Clock Enable"]
371    #[inline(always)]
372    pub fn cen(&self) -> CenR {
373        CenR::new(((self.bits >> 9) & 1) != 0)
374    }
375    #[doc = "Bits 12:15 - Prescaler Select"]
376    #[inline(always)]
377    pub fn psel(&self) -> PselR {
378        PselR::new(((self.bits >> 12) & 0x0f) as u8)
379    }
380    #[doc = "Bits 16:21 - BOD33 Threshold Level"]
381    #[inline(always)]
382    pub fn level(&self) -> LevelR {
383        LevelR::new(((self.bits >> 16) & 0x3f) as u8)
384    }
385}
386impl W {
387    #[doc = "Bit 1 - Enable"]
388    #[inline(always)]
389    #[must_use]
390    pub fn enable(&mut self) -> EnableW<Bod33Spec> {
391        EnableW::new(self, 1)
392    }
393    #[doc = "Bit 2 - Hysteresis"]
394    #[inline(always)]
395    #[must_use]
396    pub fn hyst(&mut self) -> HystW<Bod33Spec> {
397        HystW::new(self, 2)
398    }
399    #[doc = "Bits 3:4 - BOD33 Action"]
400    #[inline(always)]
401    #[must_use]
402    pub fn action(&mut self) -> ActionW<Bod33Spec> {
403        ActionW::new(self, 3)
404    }
405    #[doc = "Bit 6 - Run in Standby"]
406    #[inline(always)]
407    #[must_use]
408    pub fn runstdby(&mut self) -> RunstdbyW<Bod33Spec> {
409        RunstdbyW::new(self, 6)
410    }
411    #[doc = "Bit 8 - Operation Mode"]
412    #[inline(always)]
413    #[must_use]
414    pub fn mode(&mut self) -> ModeW<Bod33Spec> {
415        ModeW::new(self, 8)
416    }
417    #[doc = "Bit 9 - Clock Enable"]
418    #[inline(always)]
419    #[must_use]
420    pub fn cen(&mut self) -> CenW<Bod33Spec> {
421        CenW::new(self, 9)
422    }
423    #[doc = "Bits 12:15 - Prescaler Select"]
424    #[inline(always)]
425    #[must_use]
426    pub fn psel(&mut self) -> PselW<Bod33Spec> {
427        PselW::new(self, 12)
428    }
429    #[doc = "Bits 16:21 - BOD33 Threshold Level"]
430    #[inline(always)]
431    #[must_use]
432    pub fn level(&mut self) -> LevelW<Bod33Spec> {
433        LevelW::new(self, 16)
434    }
435}
436#[doc = "3.3V Brown-Out Detector (BOD33) Control\n\nYou can [`read`](crate::Reg::read) this register and get [`bod33::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bod33::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
437pub struct Bod33Spec;
438impl crate::RegisterSpec for Bod33Spec {
439    type Ux = u32;
440}
441#[doc = "`read()` method returns [`bod33::R`](R) reader structure"]
442impl crate::Readable for Bod33Spec {}
443#[doc = "`write(|w| ..)` method takes [`bod33::W`](W) writer structure"]
444impl crate::Writable for Bod33Spec {
445    type Safety = crate::Unsafe;
446    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
447    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
448}
449#[doc = "`reset()` method sets BOD33 to value 0"]
450impl crate::Resettable for Bod33Spec {
451    const RESET_VALUE: u32 = 0;
452}
atsamd21j/sysctrl/bod33.rs

atsamd21j/sysctrl/
bod33.rs
