atsamd21j/i2s/
intenset.rs

Help
1#[doc = "Register `INTENSET` reader"]
2pub type R = crate::R<IntensetSpec>;
3#[doc = "Register `INTENSET` writer"]
4pub type W = crate::W<IntensetSpec>;
5#[doc = "Field `RXRDY0` reader - Receive Ready 0 Interrupt Enable"]
6pub type Rxrdy0R = crate::BitReader;
7#[doc = "Field `RXRDY0` writer - Receive Ready 0 Interrupt Enable"]
8pub type Rxrdy0W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `RXRDY1` reader - Receive Ready 1 Interrupt Enable"]
10pub type Rxrdy1R = crate::BitReader;
11#[doc = "Field `RXRDY1` writer - Receive Ready 1 Interrupt Enable"]
12pub type Rxrdy1W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `RXOR0` reader - Receive Overrun 0 Interrupt Enable"]
14pub type Rxor0R = crate::BitReader;
15#[doc = "Field `RXOR0` writer - Receive Overrun 0 Interrupt Enable"]
16pub type Rxor0W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `RXOR1` reader - Receive Overrun 1 Interrupt Enable"]
18pub type Rxor1R = crate::BitReader;
19#[doc = "Field `RXOR1` writer - Receive Overrun 1 Interrupt Enable"]
20pub type Rxor1W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `TXRDY0` reader - Transmit Ready 0 Interrupt Enable"]
22pub type Txrdy0R = crate::BitReader;
23#[doc = "Field `TXRDY0` writer - Transmit Ready 0 Interrupt Enable"]
24pub type Txrdy0W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `TXRDY1` reader - Transmit Ready 1 Interrupt Enable"]
26pub type Txrdy1R = crate::BitReader;
27#[doc = "Field `TXRDY1` writer - Transmit Ready 1 Interrupt Enable"]
28pub type Txrdy1W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `TXUR0` reader - Transmit Underrun 0 Interrupt Enable"]
30pub type Txur0R = crate::BitReader;
31#[doc = "Field `TXUR0` writer - Transmit Underrun 0 Interrupt Enable"]
32pub type Txur0W<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `TXUR1` reader - Transmit Underrun 1 Interrupt Enable"]
34pub type Txur1R = crate::BitReader;
35#[doc = "Field `TXUR1` writer - Transmit Underrun 1 Interrupt Enable"]
36pub type Txur1W<'a, REG> = crate::BitWriter<'a, REG>;
37impl R {
38    #[doc = "Bit 0 - Receive Ready 0 Interrupt Enable"]
39    #[inline(always)]
40    pub fn rxrdy0(&self) -> Rxrdy0R {
41        Rxrdy0R::new((self.bits & 1) != 0)
42    }
43    #[doc = "Bit 1 - Receive Ready 1 Interrupt Enable"]
44    #[inline(always)]
45    pub fn rxrdy1(&self) -> Rxrdy1R {
46        Rxrdy1R::new(((self.bits >> 1) & 1) != 0)
47    }
48    #[doc = "Bit 4 - Receive Overrun 0 Interrupt Enable"]
49    #[inline(always)]
50    pub fn rxor0(&self) -> Rxor0R {
51        Rxor0R::new(((self.bits >> 4) & 1) != 0)
52    }
53    #[doc = "Bit 5 - Receive Overrun 1 Interrupt Enable"]
54    #[inline(always)]
55    pub fn rxor1(&self) -> Rxor1R {
56        Rxor1R::new(((self.bits >> 5) & 1) != 0)
57    }
58    #[doc = "Bit 8 - Transmit Ready 0 Interrupt Enable"]
59    #[inline(always)]
60    pub fn txrdy0(&self) -> Txrdy0R {
61        Txrdy0R::new(((self.bits >> 8) & 1) != 0)
62    }
63    #[doc = "Bit 9 - Transmit Ready 1 Interrupt Enable"]
64    #[inline(always)]
65    pub fn txrdy1(&self) -> Txrdy1R {
66        Txrdy1R::new(((self.bits >> 9) & 1) != 0)
67    }
68    #[doc = "Bit 12 - Transmit Underrun 0 Interrupt Enable"]
69    #[inline(always)]
70    pub fn txur0(&self) -> Txur0R {
71        Txur0R::new(((self.bits >> 12) & 1) != 0)
72    }
73    #[doc = "Bit 13 - Transmit Underrun 1 Interrupt Enable"]
74    #[inline(always)]
75    pub fn txur1(&self) -> Txur1R {
76        Txur1R::new(((self.bits >> 13) & 1) != 0)
77    }
78}
79impl W {
80    #[doc = "Bit 0 - Receive Ready 0 Interrupt Enable"]
81    #[inline(always)]
82    #[must_use]
83    pub fn rxrdy0(&mut self) -> Rxrdy0W<IntensetSpec> {
84        Rxrdy0W::new(self, 0)
85    }
86    #[doc = "Bit 1 - Receive Ready 1 Interrupt Enable"]
87    #[inline(always)]
88    #[must_use]
89    pub fn rxrdy1(&mut self) -> Rxrdy1W<IntensetSpec> {
90        Rxrdy1W::new(self, 1)
91    }
92    #[doc = "Bit 4 - Receive Overrun 0 Interrupt Enable"]
93    #[inline(always)]
94    #[must_use]
95    pub fn rxor0(&mut self) -> Rxor0W<IntensetSpec> {
96        Rxor0W::new(self, 4)
97    }
98    #[doc = "Bit 5 - Receive Overrun 1 Interrupt Enable"]
99    #[inline(always)]
100    #[must_use]
101    pub fn rxor1(&mut self) -> Rxor1W<IntensetSpec> {
102        Rxor1W::new(self, 5)
103    }
104    #[doc = "Bit 8 - Transmit Ready 0 Interrupt Enable"]
105    #[inline(always)]
106    #[must_use]
107    pub fn txrdy0(&mut self) -> Txrdy0W<IntensetSpec> {
108        Txrdy0W::new(self, 8)
109    }
110    #[doc = "Bit 9 - Transmit Ready 1 Interrupt Enable"]
111    #[inline(always)]
112    #[must_use]
113    pub fn txrdy1(&mut self) -> Txrdy1W<IntensetSpec> {
114        Txrdy1W::new(self, 9)
115    }
116    #[doc = "Bit 12 - Transmit Underrun 0 Interrupt Enable"]
117    #[inline(always)]
118    #[must_use]
119    pub fn txur0(&mut self) -> Txur0W<IntensetSpec> {
120        Txur0W::new(self, 12)
121    }
122    #[doc = "Bit 13 - Transmit Underrun 1 Interrupt Enable"]
123    #[inline(always)]
124    #[must_use]
125    pub fn txur1(&mut self) -> Txur1W<IntensetSpec> {
126        Txur1W::new(self, 13)
127    }
128}
129#[doc = "Interrupt Enable Set\n\nYou can [`read`](crate::Reg::read) this register and get [`intenset::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intenset::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
130pub struct IntensetSpec;
131impl crate::RegisterSpec for IntensetSpec {
132    type Ux = u16;
133}
134#[doc = "`read()` method returns [`intenset::R`](R) reader structure"]
135impl crate::Readable for IntensetSpec {}
136#[doc = "`write(|w| ..)` method takes [`intenset::W`](W) writer structure"]
137impl crate::Writable for IntensetSpec {
138    type Safety = crate::Unsafe;
139    const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0;
140    const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0;
141}
142#[doc = "`reset()` method sets INTENSET to value 0"]
143impl crate::Resettable for IntensetSpec {
144    const RESET_VALUE: u16 = 0;
145}
atsamd21j/i2s/intenset.rs

atsamd21j/i2s/
intenset.rs
