atsamd21j/sercom0/spi/
intenset.rs

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1#[doc = "Register `INTENSET` reader"]
2pub type R = crate::R<IntensetSpec>;
3#[doc = "Register `INTENSET` writer"]
4pub type W = crate::W<IntensetSpec>;
5#[doc = "Field `DRE` reader - Data Register Empty Interrupt Enable"]
6pub type DreR = crate::BitReader;
7#[doc = "Field `DRE` writer - Data Register Empty Interrupt Enable"]
8pub type DreW<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `TXC` reader - Transmit Complete Interrupt Enable"]
10pub type TxcR = crate::BitReader;
11#[doc = "Field `TXC` writer - Transmit Complete Interrupt Enable"]
12pub type TxcW<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `RXC` reader - Receive Complete Interrupt Enable"]
14pub type RxcR = crate::BitReader;
15#[doc = "Field `RXC` writer - Receive Complete Interrupt Enable"]
16pub type RxcW<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `SSL` reader - Slave Select Low Interrupt Enable"]
18pub type SslR = crate::BitReader;
19#[doc = "Field `SSL` writer - Slave Select Low Interrupt Enable"]
20pub type SslW<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `ERROR` reader - Combined Error Interrupt Enable"]
22pub type ErrorR = crate::BitReader;
23#[doc = "Field `ERROR` writer - Combined Error Interrupt Enable"]
24pub type ErrorW<'a, REG> = crate::BitWriter<'a, REG>;
25impl R {
26    #[doc = "Bit 0 - Data Register Empty Interrupt Enable"]
27    #[inline(always)]
28    pub fn dre(&self) -> DreR {
29        DreR::new((self.bits & 1) != 0)
30    }
31    #[doc = "Bit 1 - Transmit Complete Interrupt Enable"]
32    #[inline(always)]
33    pub fn txc(&self) -> TxcR {
34        TxcR::new(((self.bits >> 1) & 1) != 0)
35    }
36    #[doc = "Bit 2 - Receive Complete Interrupt Enable"]
37    #[inline(always)]
38    pub fn rxc(&self) -> RxcR {
39        RxcR::new(((self.bits >> 2) & 1) != 0)
40    }
41    #[doc = "Bit 3 - Slave Select Low Interrupt Enable"]
42    #[inline(always)]
43    pub fn ssl(&self) -> SslR {
44        SslR::new(((self.bits >> 3) & 1) != 0)
45    }
46    #[doc = "Bit 7 - Combined Error Interrupt Enable"]
47    #[inline(always)]
48    pub fn error(&self) -> ErrorR {
49        ErrorR::new(((self.bits >> 7) & 1) != 0)
50    }
51}
52impl W {
53    #[doc = "Bit 0 - Data Register Empty Interrupt Enable"]
54    #[inline(always)]
55    #[must_use]
56    pub fn dre(&mut self) -> DreW<IntensetSpec> {
57        DreW::new(self, 0)
58    }
59    #[doc = "Bit 1 - Transmit Complete Interrupt Enable"]
60    #[inline(always)]
61    #[must_use]
62    pub fn txc(&mut self) -> TxcW<IntensetSpec> {
63        TxcW::new(self, 1)
64    }
65    #[doc = "Bit 2 - Receive Complete Interrupt Enable"]
66    #[inline(always)]
67    #[must_use]
68    pub fn rxc(&mut self) -> RxcW<IntensetSpec> {
69        RxcW::new(self, 2)
70    }
71    #[doc = "Bit 3 - Slave Select Low Interrupt Enable"]
72    #[inline(always)]
73    #[must_use]
74    pub fn ssl(&mut self) -> SslW<IntensetSpec> {
75        SslW::new(self, 3)
76    }
77    #[doc = "Bit 7 - Combined Error Interrupt Enable"]
78    #[inline(always)]
79    #[must_use]
80    pub fn error(&mut self) -> ErrorW<IntensetSpec> {
81        ErrorW::new(self, 7)
82    }
83}
84#[doc = "SPI Interrupt Enable Set\n\nYou can [`read`](crate::Reg::read) this register and get [`intenset::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intenset::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
85pub struct IntensetSpec;
86impl crate::RegisterSpec for IntensetSpec {
87    type Ux = u8;
88}
89#[doc = "`read()` method returns [`intenset::R`](R) reader structure"]
90impl crate::Readable for IntensetSpec {}
91#[doc = "`write(|w| ..)` method takes [`intenset::W`](W) writer structure"]
92impl crate::Writable for IntensetSpec {
93    type Safety = crate::Unsafe;
94    const ZERO_TO_MODIFY_FIELDS_BITMAP: u8 = 0;
95    const ONE_TO_MODIFY_FIELDS_BITMAP: u8 = 0;
96}
97#[doc = "`reset()` method sets INTENSET to value 0"]
98impl crate::Resettable for IntensetSpec {
99    const RESET_VALUE: u8 = 0;
100}
atsamd21j/sercom0/spi/intenset.rs

atsamd21j/sercom0/spi/
intenset.rs
