atsamd21j/adc/
intenclr.rs

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1#[doc = "Register `INTENCLR` reader"]
2pub type R = crate::R<IntenclrSpec>;
3#[doc = "Register `INTENCLR` writer"]
4pub type W = crate::W<IntenclrSpec>;
5#[doc = "Field `RESRDY` reader - Result Ready Interrupt Enable"]
6pub type ResrdyR = crate::BitReader;
7#[doc = "Field `RESRDY` writer - Result Ready Interrupt Enable"]
8pub type ResrdyW<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `OVERRUN` reader - Overrun Interrupt Enable"]
10pub type OverrunR = crate::BitReader;
11#[doc = "Field `OVERRUN` writer - Overrun Interrupt Enable"]
12pub type OverrunW<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `WINMON` reader - Window Monitor Interrupt Enable"]
14pub type WinmonR = crate::BitReader;
15#[doc = "Field `WINMON` writer - Window Monitor Interrupt Enable"]
16pub type WinmonW<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `SYNCRDY` reader - Synchronization Ready Interrupt Enable"]
18pub type SyncrdyR = crate::BitReader;
19#[doc = "Field `SYNCRDY` writer - Synchronization Ready Interrupt Enable"]
20pub type SyncrdyW<'a, REG> = crate::BitWriter<'a, REG>;
21impl R {
22    #[doc = "Bit 0 - Result Ready Interrupt Enable"]
23    #[inline(always)]
24    pub fn resrdy(&self) -> ResrdyR {
25        ResrdyR::new((self.bits & 1) != 0)
26    }
27    #[doc = "Bit 1 - Overrun Interrupt Enable"]
28    #[inline(always)]
29    pub fn overrun(&self) -> OverrunR {
30        OverrunR::new(((self.bits >> 1) & 1) != 0)
31    }
32    #[doc = "Bit 2 - Window Monitor Interrupt Enable"]
33    #[inline(always)]
34    pub fn winmon(&self) -> WinmonR {
35        WinmonR::new(((self.bits >> 2) & 1) != 0)
36    }
37    #[doc = "Bit 3 - Synchronization Ready Interrupt Enable"]
38    #[inline(always)]
39    pub fn syncrdy(&self) -> SyncrdyR {
40        SyncrdyR::new(((self.bits >> 3) & 1) != 0)
41    }
42}
43impl W {
44    #[doc = "Bit 0 - Result Ready Interrupt Enable"]
45    #[inline(always)]
46    #[must_use]
47    pub fn resrdy(&mut self) -> ResrdyW<IntenclrSpec> {
48        ResrdyW::new(self, 0)
49    }
50    #[doc = "Bit 1 - Overrun Interrupt Enable"]
51    #[inline(always)]
52    #[must_use]
53    pub fn overrun(&mut self) -> OverrunW<IntenclrSpec> {
54        OverrunW::new(self, 1)
55    }
56    #[doc = "Bit 2 - Window Monitor Interrupt Enable"]
57    #[inline(always)]
58    #[must_use]
59    pub fn winmon(&mut self) -> WinmonW<IntenclrSpec> {
60        WinmonW::new(self, 2)
61    }
62    #[doc = "Bit 3 - Synchronization Ready Interrupt Enable"]
63    #[inline(always)]
64    #[must_use]
65    pub fn syncrdy(&mut self) -> SyncrdyW<IntenclrSpec> {
66        SyncrdyW::new(self, 3)
67    }
68}
69#[doc = "Interrupt Enable Clear\n\nYou can [`read`](crate::Reg::read) this register and get [`intenclr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intenclr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
70pub struct IntenclrSpec;
71impl crate::RegisterSpec for IntenclrSpec {
72    type Ux = u8;
73}
74#[doc = "`read()` method returns [`intenclr::R`](R) reader structure"]
75impl crate::Readable for IntenclrSpec {}
76#[doc = "`write(|w| ..)` method takes [`intenclr::W`](W) writer structure"]
77impl crate::Writable for IntenclrSpec {
78    type Safety = crate::Unsafe;
79    const ZERO_TO_MODIFY_FIELDS_BITMAP: u8 = 0;
80    const ONE_TO_MODIFY_FIELDS_BITMAP: u8 = 0;
81}
82#[doc = "`reset()` method sets INTENCLR to value 0"]
83impl crate::Resettable for IntenclrSpec {
84    const RESET_VALUE: u8 = 0;
85}
atsamd21j/adc/intenclr.rs

atsamd21j/adc/
intenclr.rs
