atsamd21j/usb/host/
intenclr.rs

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1#[doc = "Register `INTENCLR` reader"]
2pub type R = crate::R<IntenclrSpec>;
3#[doc = "Register `INTENCLR` writer"]
4pub type W = crate::W<IntenclrSpec>;
5#[doc = "Field `HSOF` reader - Host Start Of Frame Interrupt Disable"]
6pub type HsofR = crate::BitReader;
7#[doc = "Field `HSOF` writer - Host Start Of Frame Interrupt Disable"]
8pub type HsofW<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `RST` reader - BUS Reset Interrupt Disable"]
10pub type RstR = crate::BitReader;
11#[doc = "Field `RST` writer - BUS Reset Interrupt Disable"]
12pub type RstW<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `WAKEUP` reader - Wake Up Interrupt Disable"]
14pub type WakeupR = crate::BitReader;
15#[doc = "Field `WAKEUP` writer - Wake Up Interrupt Disable"]
16pub type WakeupW<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `DNRSM` reader - DownStream to Device Interrupt Disable"]
18pub type DnrsmR = crate::BitReader;
19#[doc = "Field `DNRSM` writer - DownStream to Device Interrupt Disable"]
20pub type DnrsmW<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `UPRSM` reader - Upstream Resume from Device Interrupt Disable"]
22pub type UprsmR = crate::BitReader;
23#[doc = "Field `UPRSM` writer - Upstream Resume from Device Interrupt Disable"]
24pub type UprsmW<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `RAMACER` reader - Ram Access Interrupt Disable"]
26pub type RamacerR = crate::BitReader;
27#[doc = "Field `RAMACER` writer - Ram Access Interrupt Disable"]
28pub type RamacerW<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `DCONN` reader - Device Connection Interrupt Disable"]
30pub type DconnR = crate::BitReader;
31#[doc = "Field `DCONN` writer - Device Connection Interrupt Disable"]
32pub type DconnW<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `DDISC` reader - Device Disconnection Interrupt Disable"]
34pub type DdiscR = crate::BitReader;
35#[doc = "Field `DDISC` writer - Device Disconnection Interrupt Disable"]
36pub type DdiscW<'a, REG> = crate::BitWriter<'a, REG>;
37impl R {
38    #[doc = "Bit 2 - Host Start Of Frame Interrupt Disable"]
39    #[inline(always)]
40    pub fn hsof(&self) -> HsofR {
41        HsofR::new(((self.bits >> 2) & 1) != 0)
42    }
43    #[doc = "Bit 3 - BUS Reset Interrupt Disable"]
44    #[inline(always)]
45    pub fn rst(&self) -> RstR {
46        RstR::new(((self.bits >> 3) & 1) != 0)
47    }
48    #[doc = "Bit 4 - Wake Up Interrupt Disable"]
49    #[inline(always)]
50    pub fn wakeup(&self) -> WakeupR {
51        WakeupR::new(((self.bits >> 4) & 1) != 0)
52    }
53    #[doc = "Bit 5 - DownStream to Device Interrupt Disable"]
54    #[inline(always)]
55    pub fn dnrsm(&self) -> DnrsmR {
56        DnrsmR::new(((self.bits >> 5) & 1) != 0)
57    }
58    #[doc = "Bit 6 - Upstream Resume from Device Interrupt Disable"]
59    #[inline(always)]
60    pub fn uprsm(&self) -> UprsmR {
61        UprsmR::new(((self.bits >> 6) & 1) != 0)
62    }
63    #[doc = "Bit 7 - Ram Access Interrupt Disable"]
64    #[inline(always)]
65    pub fn ramacer(&self) -> RamacerR {
66        RamacerR::new(((self.bits >> 7) & 1) != 0)
67    }
68    #[doc = "Bit 8 - Device Connection Interrupt Disable"]
69    #[inline(always)]
70    pub fn dconn(&self) -> DconnR {
71        DconnR::new(((self.bits >> 8) & 1) != 0)
72    }
73    #[doc = "Bit 9 - Device Disconnection Interrupt Disable"]
74    #[inline(always)]
75    pub fn ddisc(&self) -> DdiscR {
76        DdiscR::new(((self.bits >> 9) & 1) != 0)
77    }
78}
79impl W {
80    #[doc = "Bit 2 - Host Start Of Frame Interrupt Disable"]
81    #[inline(always)]
82    #[must_use]
83    pub fn hsof(&mut self) -> HsofW<IntenclrSpec> {
84        HsofW::new(self, 2)
85    }
86    #[doc = "Bit 3 - BUS Reset Interrupt Disable"]
87    #[inline(always)]
88    #[must_use]
89    pub fn rst(&mut self) -> RstW<IntenclrSpec> {
90        RstW::new(self, 3)
91    }
92    #[doc = "Bit 4 - Wake Up Interrupt Disable"]
93    #[inline(always)]
94    #[must_use]
95    pub fn wakeup(&mut self) -> WakeupW<IntenclrSpec> {
96        WakeupW::new(self, 4)
97    }
98    #[doc = "Bit 5 - DownStream to Device Interrupt Disable"]
99    #[inline(always)]
100    #[must_use]
101    pub fn dnrsm(&mut self) -> DnrsmW<IntenclrSpec> {
102        DnrsmW::new(self, 5)
103    }
104    #[doc = "Bit 6 - Upstream Resume from Device Interrupt Disable"]
105    #[inline(always)]
106    #[must_use]
107    pub fn uprsm(&mut self) -> UprsmW<IntenclrSpec> {
108        UprsmW::new(self, 6)
109    }
110    #[doc = "Bit 7 - Ram Access Interrupt Disable"]
111    #[inline(always)]
112    #[must_use]
113    pub fn ramacer(&mut self) -> RamacerW<IntenclrSpec> {
114        RamacerW::new(self, 7)
115    }
116    #[doc = "Bit 8 - Device Connection Interrupt Disable"]
117    #[inline(always)]
118    #[must_use]
119    pub fn dconn(&mut self) -> DconnW<IntenclrSpec> {
120        DconnW::new(self, 8)
121    }
122    #[doc = "Bit 9 - Device Disconnection Interrupt Disable"]
123    #[inline(always)]
124    #[must_use]
125    pub fn ddisc(&mut self) -> DdiscW<IntenclrSpec> {
126        DdiscW::new(self, 9)
127    }
128}
129#[doc = "HOST Host Interrupt Enable Clear\n\nYou can [`read`](crate::Reg::read) this register and get [`intenclr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intenclr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
130pub struct IntenclrSpec;
131impl crate::RegisterSpec for IntenclrSpec {
132    type Ux = u16;
133}
134#[doc = "`read()` method returns [`intenclr::R`](R) reader structure"]
135impl crate::Readable for IntenclrSpec {}
136#[doc = "`write(|w| ..)` method takes [`intenclr::W`](W) writer structure"]
137impl crate::Writable for IntenclrSpec {
138    type Safety = crate::Unsafe;
139    const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0;
140    const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0;
141}
142#[doc = "`reset()` method sets INTENCLR to value 0"]
143impl crate::Resettable for IntenclrSpec {
144    const RESET_VALUE: u16 = 0;
145}
atsamd21j/usb/host/intenclr.rs

atsamd21j/usb/host/
intenclr.rs
