atsamd21j/rtc/mode1/
ctrl.rs

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1#[doc = "Register `CTRL` reader"]
2pub type R = crate::R<CtrlSpec>;
3#[doc = "Register `CTRL` writer"]
4pub type W = crate::W<CtrlSpec>;
5#[doc = "Field `SWRST` reader - Software Reset"]
6pub type SwrstR = crate::BitReader;
7#[doc = "Field `SWRST` writer - Software Reset"]
8pub type SwrstW<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `ENABLE` reader - Enable"]
10pub type EnableR = crate::BitReader;
11#[doc = "Field `ENABLE` writer - Enable"]
12pub type EnableW<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Operating Mode\n\nValue on reset: 0"]
14#[derive(Clone, Copy, Debug, PartialEq, Eq)]
15#[repr(u8)]
16pub enum Modeselect {
17    #[doc = "0: Mode 0: 32-bit Counter"]
18    Count32 = 0,
19    #[doc = "1: Mode 1: 16-bit Counter"]
20    Count16 = 1,
21    #[doc = "2: Mode 2: Clock/Calendar"]
22    Clock = 2,
23}
24impl From<Modeselect> for u8 {
25    #[inline(always)]
26    fn from(variant: Modeselect) -> Self {
27        variant as _
28    }
29}
30impl crate::FieldSpec for Modeselect {
31    type Ux = u8;
32}
33impl crate::IsEnum for Modeselect {}
34#[doc = "Field `MODE` reader - Operating Mode"]
35pub type ModeR = crate::FieldReader<Modeselect>;
36impl ModeR {
37    #[doc = "Get enumerated values variant"]
38    #[inline(always)]
39    pub const fn variant(&self) -> Option<Modeselect> {
40        match self.bits {
41            0 => Some(Modeselect::Count32),
42            1 => Some(Modeselect::Count16),
43            2 => Some(Modeselect::Clock),
44            _ => None,
45        }
46    }
47    #[doc = "Mode 0: 32-bit Counter"]
48    #[inline(always)]
49    pub fn is_count32(&self) -> bool {
50        *self == Modeselect::Count32
51    }
52    #[doc = "Mode 1: 16-bit Counter"]
53    #[inline(always)]
54    pub fn is_count16(&self) -> bool {
55        *self == Modeselect::Count16
56    }
57    #[doc = "Mode 2: Clock/Calendar"]
58    #[inline(always)]
59    pub fn is_clock(&self) -> bool {
60        *self == Modeselect::Clock
61    }
62}
63#[doc = "Field `MODE` writer - Operating Mode"]
64pub type ModeW<'a, REG> = crate::FieldWriter<'a, REG, 2, Modeselect>;
65impl<'a, REG> ModeW<'a, REG>
66where
67    REG: crate::Writable + crate::RegisterSpec,
68    REG::Ux: From<u8>,
69{
70    #[doc = "Mode 0: 32-bit Counter"]
71    #[inline(always)]
72    pub fn count32(self) -> &'a mut crate::W<REG> {
73        self.variant(Modeselect::Count32)
74    }
75    #[doc = "Mode 1: 16-bit Counter"]
76    #[inline(always)]
77    pub fn count16(self) -> &'a mut crate::W<REG> {
78        self.variant(Modeselect::Count16)
79    }
80    #[doc = "Mode 2: Clock/Calendar"]
81    #[inline(always)]
82    pub fn clock(self) -> &'a mut crate::W<REG> {
83        self.variant(Modeselect::Clock)
84    }
85}
86#[doc = "Prescaler\n\nValue on reset: 0"]
87#[derive(Clone, Copy, Debug, PartialEq, Eq)]
88#[repr(u8)]
89pub enum Prescalerselect {
90    #[doc = "0: CLK_RTC_CNT = GCLK_RTC/1"]
91    Div1 = 0,
92    #[doc = "1: CLK_RTC_CNT = GCLK_RTC/2"]
93    Div2 = 1,
94    #[doc = "2: CLK_RTC_CNT = GCLK_RTC/4"]
95    Div4 = 2,
96    #[doc = "3: CLK_RTC_CNT = GCLK_RTC/8"]
97    Div8 = 3,
98    #[doc = "4: CLK_RTC_CNT = GCLK_RTC/16"]
99    Div16 = 4,
100    #[doc = "5: CLK_RTC_CNT = GCLK_RTC/32"]
101    Div32 = 5,
102    #[doc = "6: CLK_RTC_CNT = GCLK_RTC/64"]
103    Div64 = 6,
104    #[doc = "7: CLK_RTC_CNT = GCLK_RTC/128"]
105    Div128 = 7,
106    #[doc = "8: CLK_RTC_CNT = GCLK_RTC/256"]
107    Div256 = 8,
108    #[doc = "9: CLK_RTC_CNT = GCLK_RTC/512"]
109    Div512 = 9,
110    #[doc = "10: CLK_RTC_CNT = GCLK_RTC/1024"]
111    Div1024 = 10,
112}
113impl From<Prescalerselect> for u8 {
114    #[inline(always)]
115    fn from(variant: Prescalerselect) -> Self {
116        variant as _
117    }
118}
119impl crate::FieldSpec for Prescalerselect {
120    type Ux = u8;
121}
122impl crate::IsEnum for Prescalerselect {}
123#[doc = "Field `PRESCALER` reader - Prescaler"]
124pub type PrescalerR = crate::FieldReader<Prescalerselect>;
125impl PrescalerR {
126    #[doc = "Get enumerated values variant"]
127    #[inline(always)]
128    pub const fn variant(&self) -> Option<Prescalerselect> {
129        match self.bits {
130            0 => Some(Prescalerselect::Div1),
131            1 => Some(Prescalerselect::Div2),
132            2 => Some(Prescalerselect::Div4),
133            3 => Some(Prescalerselect::Div8),
134            4 => Some(Prescalerselect::Div16),
135            5 => Some(Prescalerselect::Div32),
136            6 => Some(Prescalerselect::Div64),
137            7 => Some(Prescalerselect::Div128),
138            8 => Some(Prescalerselect::Div256),
139            9 => Some(Prescalerselect::Div512),
140            10 => Some(Prescalerselect::Div1024),
141            _ => None,
142        }
143    }
144    #[doc = "CLK_RTC_CNT = GCLK_RTC/1"]
145    #[inline(always)]
146    pub fn is_div1(&self) -> bool {
147        *self == Prescalerselect::Div1
148    }
149    #[doc = "CLK_RTC_CNT = GCLK_RTC/2"]
150    #[inline(always)]
151    pub fn is_div2(&self) -> bool {
152        *self == Prescalerselect::Div2
153    }
154    #[doc = "CLK_RTC_CNT = GCLK_RTC/4"]
155    #[inline(always)]
156    pub fn is_div4(&self) -> bool {
157        *self == Prescalerselect::Div4
158    }
159    #[doc = "CLK_RTC_CNT = GCLK_RTC/8"]
160    #[inline(always)]
161    pub fn is_div8(&self) -> bool {
162        *self == Prescalerselect::Div8
163    }
164    #[doc = "CLK_RTC_CNT = GCLK_RTC/16"]
165    #[inline(always)]
166    pub fn is_div16(&self) -> bool {
167        *self == Prescalerselect::Div16
168    }
169    #[doc = "CLK_RTC_CNT = GCLK_RTC/32"]
170    #[inline(always)]
171    pub fn is_div32(&self) -> bool {
172        *self == Prescalerselect::Div32
173    }
174    #[doc = "CLK_RTC_CNT = GCLK_RTC/64"]
175    #[inline(always)]
176    pub fn is_div64(&self) -> bool {
177        *self == Prescalerselect::Div64
178    }
179    #[doc = "CLK_RTC_CNT = GCLK_RTC/128"]
180    #[inline(always)]
181    pub fn is_div128(&self) -> bool {
182        *self == Prescalerselect::Div128
183    }
184    #[doc = "CLK_RTC_CNT = GCLK_RTC/256"]
185    #[inline(always)]
186    pub fn is_div256(&self) -> bool {
187        *self == Prescalerselect::Div256
188    }
189    #[doc = "CLK_RTC_CNT = GCLK_RTC/512"]
190    #[inline(always)]
191    pub fn is_div512(&self) -> bool {
192        *self == Prescalerselect::Div512
193    }
194    #[doc = "CLK_RTC_CNT = GCLK_RTC/1024"]
195    #[inline(always)]
196    pub fn is_div1024(&self) -> bool {
197        *self == Prescalerselect::Div1024
198    }
199}
200#[doc = "Field `PRESCALER` writer - Prescaler"]
201pub type PrescalerW<'a, REG> = crate::FieldWriter<'a, REG, 4, Prescalerselect>;
202impl<'a, REG> PrescalerW<'a, REG>
203where
204    REG: crate::Writable + crate::RegisterSpec,
205    REG::Ux: From<u8>,
206{
207    #[doc = "CLK_RTC_CNT = GCLK_RTC/1"]
208    #[inline(always)]
209    pub fn div1(self) -> &'a mut crate::W<REG> {
210        self.variant(Prescalerselect::Div1)
211    }
212    #[doc = "CLK_RTC_CNT = GCLK_RTC/2"]
213    #[inline(always)]
214    pub fn div2(self) -> &'a mut crate::W<REG> {
215        self.variant(Prescalerselect::Div2)
216    }
217    #[doc = "CLK_RTC_CNT = GCLK_RTC/4"]
218    #[inline(always)]
219    pub fn div4(self) -> &'a mut crate::W<REG> {
220        self.variant(Prescalerselect::Div4)
221    }
222    #[doc = "CLK_RTC_CNT = GCLK_RTC/8"]
223    #[inline(always)]
224    pub fn div8(self) -> &'a mut crate::W<REG> {
225        self.variant(Prescalerselect::Div8)
226    }
227    #[doc = "CLK_RTC_CNT = GCLK_RTC/16"]
228    #[inline(always)]
229    pub fn div16(self) -> &'a mut crate::W<REG> {
230        self.variant(Prescalerselect::Div16)
231    }
232    #[doc = "CLK_RTC_CNT = GCLK_RTC/32"]
233    #[inline(always)]
234    pub fn div32(self) -> &'a mut crate::W<REG> {
235        self.variant(Prescalerselect::Div32)
236    }
237    #[doc = "CLK_RTC_CNT = GCLK_RTC/64"]
238    #[inline(always)]
239    pub fn div64(self) -> &'a mut crate::W<REG> {
240        self.variant(Prescalerselect::Div64)
241    }
242    #[doc = "CLK_RTC_CNT = GCLK_RTC/128"]
243    #[inline(always)]
244    pub fn div128(self) -> &'a mut crate::W<REG> {
245        self.variant(Prescalerselect::Div128)
246    }
247    #[doc = "CLK_RTC_CNT = GCLK_RTC/256"]
248    #[inline(always)]
249    pub fn div256(self) -> &'a mut crate::W<REG> {
250        self.variant(Prescalerselect::Div256)
251    }
252    #[doc = "CLK_RTC_CNT = GCLK_RTC/512"]
253    #[inline(always)]
254    pub fn div512(self) -> &'a mut crate::W<REG> {
255        self.variant(Prescalerselect::Div512)
256    }
257    #[doc = "CLK_RTC_CNT = GCLK_RTC/1024"]
258    #[inline(always)]
259    pub fn div1024(self) -> &'a mut crate::W<REG> {
260        self.variant(Prescalerselect::Div1024)
261    }
262}
263impl R {
264    #[doc = "Bit 0 - Software Reset"]
265    #[inline(always)]
266    pub fn swrst(&self) -> SwrstR {
267        SwrstR::new((self.bits & 1) != 0)
268    }
269    #[doc = "Bit 1 - Enable"]
270    #[inline(always)]
271    pub fn enable(&self) -> EnableR {
272        EnableR::new(((self.bits >> 1) & 1) != 0)
273    }
274    #[doc = "Bits 2:3 - Operating Mode"]
275    #[inline(always)]
276    pub fn mode(&self) -> ModeR {
277        ModeR::new(((self.bits >> 2) & 3) as u8)
278    }
279    #[doc = "Bits 8:11 - Prescaler"]
280    #[inline(always)]
281    pub fn prescaler(&self) -> PrescalerR {
282        PrescalerR::new(((self.bits >> 8) & 0x0f) as u8)
283    }
284}
285impl W {
286    #[doc = "Bit 0 - Software Reset"]
287    #[inline(always)]
288    #[must_use]
289    pub fn swrst(&mut self) -> SwrstW<CtrlSpec> {
290        SwrstW::new(self, 0)
291    }
292    #[doc = "Bit 1 - Enable"]
293    #[inline(always)]
294    #[must_use]
295    pub fn enable(&mut self) -> EnableW<CtrlSpec> {
296        EnableW::new(self, 1)
297    }
298    #[doc = "Bits 2:3 - Operating Mode"]
299    #[inline(always)]
300    #[must_use]
301    pub fn mode(&mut self) -> ModeW<CtrlSpec> {
302        ModeW::new(self, 2)
303    }
304    #[doc = "Bits 8:11 - Prescaler"]
305    #[inline(always)]
306    #[must_use]
307    pub fn prescaler(&mut self) -> PrescalerW<CtrlSpec> {
308        PrescalerW::new(self, 8)
309    }
310}
311#[doc = "MODE1 Control\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
312pub struct CtrlSpec;
313impl crate::RegisterSpec for CtrlSpec {
314    type Ux = u16;
315}
316#[doc = "`read()` method returns [`ctrl::R`](R) reader structure"]
317impl crate::Readable for CtrlSpec {}
318#[doc = "`write(|w| ..)` method takes [`ctrl::W`](W) writer structure"]
319impl crate::Writable for CtrlSpec {
320    type Safety = crate::Unsafe;
321    const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0;
322    const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0;
323}
324#[doc = "`reset()` method sets CTRL to value 0"]
325impl crate::Resettable for CtrlSpec {
326    const RESET_VALUE: u16 = 0;
327}
atsamd21j/rtc/mode1/ctrl.rs

atsamd21j/rtc/mode1/
ctrl.rs
